公开(公告)号：US20210408222A1

公开(公告)日：2021-12-30

申请号：US17142813

申请日：2021-01-06

Applicant: SK hynix Inc.

Inventor： Dong Ik SUH ,  Se Ho LEE

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/51

Abstract: A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher.

公开(公告)号：US20210257407A1

公开(公告)日：2021-08-19

申请号：US16941155

申请日：2020-07-28

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/24 ,  H01L29/06 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, and a gate structure disposed on the substrate and including a hole pattern. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer which are alternately stacked, and the gate electrode layer protrudes toward a center of the hole pattern relative to the interlayer insulation layer. The nonvolatile memory device includes a first functional layer disposed along a sidewall surface of the gate structure inside the hole pattern, a second functional layer disposed on the first functional layer inside the hole pattern, and a channel layer extending in a direction perpendicular to the substrate inside the hole pattern and disposed to contact a cell portion of the second functional layer. The cell portion of the second functional layer indirectly covers a sidewall surface of the gate electrode layer.

公开(公告)号：US20210183890A1

公开(公告)日：2021-06-17

申请号：US17159979

申请日：2021-01-27

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Ju Ry SONG ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses.

公开(公告)号：US20200212068A1

公开(公告)日：2020-07-02

申请号：US16536063

申请日：2019-08-08

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Ju Ry SONG ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures.

公开(公告)号：US20190310921A1

公开(公告)日：2019-10-10

申请号：US16151422

申请日：2018-10-04

Applicant: SK hynix Inc.

Inventor： Se Ho LEE ,  Min Gu KANG

IPC: G06F11/14 ,  G06F12/02 ,  G06F3/06

Abstract: A data storage device may include: a storage unit comprising a storage comprising a storage area divided into a plurality of blocks, and a controller configured to control a data input/output operation on the storage according to a request of a host device, collect information on a block, of the plurality of blocks, involved in a background operation which is performed while power is supplied, store the collected information as hint information, and resume a background operation started before a sudden power-off, based on the hint information, when power is resupplied after the sudden power-off.

公开(公告)号：US20160086663A1

公开(公告)日：2016-03-24

申请号：US14956823

申请日：2015-12-02

Applicant: SK hynix Inc.

Inventor： Seung Yun LEE ,  Hae Chan PARK ,  Myoung Sub KIM ,  Se Ho LEE

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0038 ,  G11C2013/008

Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Abstract translation: 提供半导体存储装置及其温度控制方法。 半导体存储装置包括适于调节存储单元的温度的温度调节单元，以及温度调节单元，其适于感测温度调节单元的温度，将感测温度与参考温度范围进行比较，并且控制温度调节 基于比较结果在基准温度范围内调节其温度。

公开(公告)号：US20150109856A1

公开(公告)日：2015-04-23

申请号：US14158496

申请日：2014-01-17

Applicant: SK hynix Inc.

Inventor： Seung Yun LEE ,  Hae Chan PARK ,  Myoung Sub KIM ,  Se Ho LEE

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/008

Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Abstract translation: 提供半导体存储装置及其温度控制方法。 半导体存储装置包括适于调节存储单元的温度的温度调节单元，以及温度调节单元，其适于感测温度调节单元的温度，将感测温度与参考温度范围进行比较，并且控制温度调节 基于比较结果在基准温度范围内调节其温度。

公开(公告)号：US20140166965A1

公开(公告)日：2014-06-19

申请号：US13846129

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Jung Won SEO ,  Hae Chan PARK ,  Myoung Sub KIM ,  Sung Bin HONG ,  Se Ho LEE ,  Seung Yun LEE

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/1608 ,  H01L45/1666

Abstract: A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure.

Abstract translation: 电阻式存储器件可以包括底部结构，设置在底部结构上的存储单元结构，以及设置成围绕存储单元结构的外侧壁的数据存储材料。