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    High electron mobility transistor (HEMT) devices and methods
    31.
    发明授权
    High electron mobility transistor (HEMT) devices and methods 有权

    公开(公告)号：US11552189B2

    公开(公告)日：2023-01-10

    申请号：US17027118

    申请日：2020-09-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Davide Giuseppe Patti

    IPC: H01L29/778 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L27/06 ,  H01L29/43

    Abstract: Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

    Integrated semiconductor device comprising a hall effect current sensor
    38.
    发明授权
    Integrated semiconductor device comprising a hall effect current sensor 有权
    集成半导体器件，包括霍尔效应电流传感器

    公开(公告)号：US09581620B2

    公开(公告)日：2017-02-28

    申请号：US14615196

    申请日：2015-02-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dario Sutera ,  Davide Giuseppe Patti ,  Valeria Cinnera Martino

    IPC: G01R15/20 ,  G01R15/18 ,  G01R19/00 ,  G01R33/07

    CPC classification number: G01R15/202 ,  G01R15/18 ,  G01R15/207 ,  G01R19/0092 ,  G01R33/07

    Abstract: The semiconductor integrated device has a conductive region, for example, an external contact pad, configured to be traversed by a current to be measured. A concentrator of magnetic material partially surrounds the conductive region and has an annular shape open at a point defining an air gap area where a sensitive region is arranged, which is electrically conductive and is typically of doped semiconductor material, such as polycrystalline silicon. The device is integrated in a chip formed by a substrate and by an insulating layer, the sensitive region and the concentrator being formed in the insulating layer.

    Abstract translation: 半导体集成器件具有导电区域，例如外部接触焊盘，被配置为被被测量的电流穿过。 磁性材料的集中器部分地围绕导电区域并且具有在限定气隙区域的位置处的环形形状，其中布置有敏感区域，该敏感区域是导电的并且通常是掺杂半导体材料，例如多晶硅。 该器件集成在由衬底形成的芯片和绝缘层中，敏感区域和集中器形成在绝缘层中。

    Integrated vacuum microelectronic structure and manufacturing method thereof
    39.
    发明授权
    Integrated vacuum microelectronic structure and manufacturing method thereof 有权
    集成真空微电子结构及其制造方法

    公开(公告)号：US09496392B2

    公开(公告)日：2016-11-15

    申请号：US14667215

    申请日：2015-03-24

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Davide Giuseppe Patti ,  Gianleonardo Grasso

    IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/12 ,  H01L29/66 ,  H01J21/10 ,  G01K7/01

    CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

    Abstract: An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.

    Abstract translation: 集成的真空微电子结构被描述为具有高度掺杂的半导体衬底，放置在所述掺杂半导体衬底之上的第一绝缘层，放置在所述第一绝缘层之上的第一导电层，放置在所述第一导电层上方的第二绝缘层，真空 形成在所述第一和第二绝缘层内并延伸到高掺杂半导体衬底的第二导电层，置于所述真空沟槽之上并用作阴极的第二导电层，置于所述高掺杂半导体衬底之下并用作阳极的第三金属层， 所述第二导电层邻近所述真空沟槽的上边缘放置，所述第一导电层通过所述第二绝缘层的一部分与所述真空沟槽分离，并与所述第二导电层电接触。

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