公开(公告)号：US10909929B2

公开(公告)日：2021-02-02

申请号：US16210379

申请日：2018-12-05

申请人： Samsung Display Co., Ltd.

发明人： Tae Hoon Yang ,  Ki Bum Kim ,  Jong Chan Lee ,  Woong Hee Jeong

IPC分类号： G11C19/00 ,  G09G3/3266 ,  G09G3/3291 ,  G09G3/3233 ,  G09G3/3258 ,  H01L27/32 ,  G09G3/36 ,  G11C19/28

摘要： A scan driver includes stage circuits, each including: a first circuit including a control terminal (CT) connected to a first node (N1), and connecting/disconnecting a previous scan line of a previous stage circuit to a second node (N2) based on a control signal (CS); a second circuit including a CT connected to a clock signal line, and connecting one of a first power voltage line (FPVL) and a second power voltage line (SPVL) to the N1 based on a CS; a third circuit including a CT connected to the N2, and connecting one of the N1 and the SPVL to a third node (N3) based on a CS; a fourth circuit including a CT connected to the N3, and connecting one of the FPVL and the SPVL to a current scan line based on a CS; and a first capacitor connecting the CT of the third circuit and the SPVL.

公开(公告)号：US10714556B2

公开(公告)日：2020-07-14

申请号：US16296755

申请日：2019-03-08

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Woong Hee Jeong ,  Tae Hoon Yang ,  Jong Chan Lee

IPC分类号： H01L27/32 ,  G09G3/3233 ,  H01L27/12

摘要： A transistor substrate may include a base substrate, and a switching transistor and a driving transistor provided on the base substrate. The driving transistor includes: an active pattern provided on the base substrate and including a source region, a drain region spaced apart from the source region, and a channel region provided between the source region and the drain region; a gate electrode at least partially overlapping the active pattern; a gate insulating film provided between the active pattern and the gate electrode; a source electrode insulated from the gate electrode and connected to the source region; a drain electrode insulated from the gate electrode and connected to the drain region; and at least one dummy hole adjacent to the channel region.

公开(公告)号：US20190311675A1

公开(公告)日：2019-10-10

申请号：US16372296

申请日：2019-04-01

申请人： Samsung Display Co., Ltd.

发明人： Tae Hoon Yang ,  Ki Bum Kim ,  Jong Chan Lee ,  Woong Hee Jeong

IPC分类号： G09G3/3233 ,  G09G3/3266 ,  G09G3/3283 ,  H01L27/32

摘要： A pixel including a light emitting element, a first transistor connected between a first node and the light emitting element to control current flowing from a first power supply to a second power supply, a second transistor connected between a data line and the first transistor to be turned on by an ith first scan signal, a third transistor including a P-type TFT connected between the first transistor and the first node to be turned on by the ith first scan signal and, a fourth transistor including an N-type TFT connected between the first node and an initialization power supply line to be turned on by an i−1th scan signal, and a first connection line connected between the third and fourth transistors to electrically connect semiconductor patterns thereof, in which the first connection line is disposed on the third and fourth transistors and contacts the semiconductor patterns thereof.

公开(公告)号：US20190295472A1

公开(公告)日：2019-09-26

申请号：US16210379

申请日：2018-12-05

申请人： Samsung Display Co., Ltd.

发明人： Tae Hoon YANG ,  Ki Bum Kim ,  Jong Chan Lee ,  Woong Hee Jeong

IPC分类号： G09G3/3266 ,  G09G3/3291 ,  G09G3/3233 ,  G09G3/3258 ,  H01L27/32

摘要： A scan driver includes stage circuits, each including: a first circuit including a control terminal (CT) connected to a first node (N1), and connecting/disconnecting a previous scan line of a previous stage circuit to a second node (N2) based on a control signal (CS); a second circuit including a CT connected to a clock signal line, and connecting one of a first power voltage line (FPVL) and a second power voltage line (SPVL) to the N1 based on a CS; a third circuit including a CT connected to the N2, and connecting one of the N1 and the SPVL to a third node (N3) based on a CS; a fourth circuit including a CT connected to the N3, and connecting one of the FPVL and the SPVL to a current scan line based on a CS; and a first capacitor connecting the CT of the third circuit and the SPVL.

公开(公告)号：US20160148983A1

公开(公告)日：2016-05-26

申请号：US14708070

申请日：2015-05-08

申请人： Samsung Display Co., Ltd.

发明人： Myoung Geun Cha ,  Dong Jo Kim ,  Yoon Ho Khang ,  Jong Chan Lee

IPC分类号： H01L27/32 ,  H01L21/223 ,  H01L21/311

CPC分类号： H01L27/3262 ,  H01L21/31116 ,  H01L27/1225 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2227/323

摘要： An OLED display and a method of manufacturing the same are disclosed. In one aspect, the OLED display includes a substrate and a semiconductor layer formed over the substrate, wherein the semiconductor layer includes a channel and a contact region formed on opposing sides of the channel. The display also includes an insulating layer formed over the semiconductor layer and having a contact hole exposing the contact region, and an OLED formed over the insulating layer, wherein the OLED is electrically connected to the contact region through the contact hole, and wherein at least a portion of the contact hole is formed directly above the contact region.

摘要翻译： 公开了OLED显示器及其制造方法。 一方面，OLED显示器包括衬底和形成在衬底上的半导体层，其中半导体层包括通道和形成在通道的相对侧上的接触区域。 所述显示器还包括形成在所述半导体层上并具有暴露所述接触区域的接触孔的绝缘层和形成在所述绝缘层上的OLED，其中所述OLED通过所述接触孔电连接到所述接触区域，并且其中至少 接触孔的一部分直接形成在接触区域的正上方。

公开(公告)号：US20140175429A1

公开(公告)日：2014-06-26

申请号：US14070886

申请日：2013-11-04

申请人： Samsung Display Co., Ltd.

发明人： DONG JO KIM ,  Ji Seon Lee ,  Jong Chan Lee ,  Yoon Ho Khang ,  Sang Ho Park ,  Yong Su Lee ,  Jung Kyu Lee

IPC分类号： H01L27/12

CPC分类号： H01L27/1225 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288

摘要： A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

摘要翻译： 薄膜晶体管阵列面板可以包括在半导体层中形成的氧化物半导体的沟道层，形成在半导体层中并连接到第一侧的沟道层的源电极，形成在半导体层中的漏电极和 连接到相对的第二侧的沟道层，形成在与漏电极的半导体层相同的部分中的半导体层中的像素电极，设置在沟道层上的绝缘层，设置在栅电极上的栅极线 绝缘层，设置在源电极和漏电极上的钝化层，像素电极和栅极线以及设置在钝化层上的数据线。 沟道层的宽度可以基本上等于像素电极在与栅极线平行的方向上的宽度。