公开(公告)号：US11881455B2

公开(公告)日：2024-01-23

申请号：US17389622

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L27/06 ,  H01L23/532 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/485

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0694 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

公开(公告)号：US20230378164A1

公开(公告)日：2023-11-23

申请号：US18366010

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/02 ,  H01L27/07 ,  H01L29/861 ,  H01L29/739 ,  H01L21/8238

CPC classification number: H01L27/0255 ,  H01L27/0727 ,  H01L29/861 ,  H01L29/7391 ,  H01L21/823807 ,  H01L21/823885

Abstract: Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

公开(公告)号：US20230369317A1

公开(公告)日：2023-11-16

申请号：US18356545

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US11764207B2

公开(公告)日：2023-09-19

申请号：US17554171

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/02 ,  H01L27/07 ,  H01L29/861 ,  H01L21/8238 ,  H01L29/739

CPC classification number: H01L27/0255 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/0727 ,  H01L29/7391 ,  H01L29/861

Abstract: Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

公开(公告)号：US20230231015A1

公开(公告)日：2023-07-20

申请号：US18187506

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Hwichan JUN ,  Inchan Hwang ,  Byounghak Hong

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L29/0665 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/41733 ,  H01L27/088

Abstract: A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

公开(公告)号：US20230154983A1

公开(公告)日：2023-05-18

申请号：US17576726

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-ill Seo ,  Sooyoung Park ,  Byounghak Hong

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/823418 ,  H01L29/66742 ,  H01L21/823412

Abstract: A semiconductor device includes: a substrate; at least one hybrid channel structure formed on the substrate and including at least one 1st channel structure extended in 1st and 2nd directions in parallel with an upper surface of the substrate without directly contacting the substrate, and a 2nd channel structure connected to and intersecting the at least one 1st channel structure in a 3rd direction perpendicular to the 1st or 2nd direction; a gate structure surrounding the hybrid channel structure; and source/drain regions respectively formed at two opposite ends of the at least one hybrid channel structure in the 1st direction.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US11605708B2

公开(公告)日：2023-03-14

申请号：US17094920

申请日：2020-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first active region including a first vertical field effect transistor (VFET), a second active region including a second VFET, and a diffusion break between the first active region and the second active region on a substrate. The diffusion break may include first and second isolation layers in the substrate and a diffusion break channel region protruding from a portion of the substrate. The portion of the substrate may be between the first isolation layer and the second isolation layer. In some embodiments, the first and second isolation layers may be adjacent to respective opposing sidewalls of the diffusion break channel region.

公开(公告)号：US20220336473A1

公开(公告)日：2022-10-20

申请号：US17382060

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US20220302172A1

公开(公告)日：2022-09-22

申请号：US17335834

申请日：2021-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo

IPC: H01L27/12

Abstract: A multi-stack semiconductor device formed to cover a plurality of gate pitches includes: a 1st transistor; a 2nd transistor formed at a right side of the 1st transistor, and isolated from the transistor by a 1st portion of a diffusion break structure; a 3rd transistor formed vertically above or below the 1st transistor; and a 4th transistor formed at a right side of the 3rd transistor, and isolated from the 3rd transistor by a 2nd portion of the diffusion break structure, wherein the 1st portion and the 2nd portion of the diffusion break structure are formed of different material compositions or have different physical dimensions.