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公开(公告)号：US20200004652A1
公开(公告)日：2020-01-02
申请号：US16150239
申请日：2018-10-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dimin NIU , Krishna MALLADI , Hongzhong ZHENG
Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.
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公开(公告)号：US20190266050A1
公开(公告)日：2019-08-29
申请号：US16411127
申请日：2019-05-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dimin NIU , Mu-Tien CHANG , Hongzhong ZHENG , Hyun-Joong KIM , Won-Hyung SONG , Jangseok CHOI
IPC: G06F11/10 , G11C29/52 , G11C11/4093
Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.
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公开(公告)号：US20190235788A1
公开(公告)日：2019-08-01
申请号：US15949934
申请日：2018-04-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dimin NIU , Mu Tien CHANG , Hongzhong ZHENG , Sun Young LIM , Jae-Gon LEE , Indong KIM
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0644 , G06F3/0679
Abstract: A method of page size aware scheduling and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of page size aware scheduling are provided. The method includes determining a size of a media page; determining if the media page is open or closed; performing, by a memory controller, a speculative read operation if the media page is determined to be open; and performing, by the memory controller, a regular read operation if the media page is determined to be closed.
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Patent Agency Ranking
公开(公告)号：US20180122456A1
公开(公告)日：2018-05-03
申请号：US15426033
申请日：2017-02-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shaungchen LI , Dimin NIU , Krishna MALLADI , Hongzhong ZHENG
IPC: G11C11/406
CPC classification number: G11C11/40622 , G06F9/38 , G06F12/00 , G06F15/7821 , G06F15/80 , G11C7/1006 , G11C7/1012 , G11C11/405 , G11C11/4076 , G11C11/4091 , G11C11/4096
Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.
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公开(公告)号：US20170255575A1
公开(公告)日：2017-09-07
申请号：US15233850
申请日：2016-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dimin NIU , Mu-Tien CHANG , Hongzhong ZHENG , Sun Young LIM , Indong KIM , Jangseok CHOI , Craig HANSON
CPC classification number: G06F13/1673 , G06F13/4068 , G06F13/42
Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.
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公开(公告)号：US20170242595A1
公开(公告)日：2017-08-24
申请号：US15136872
申请日：2016-04-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dimin NIU , Mu-Tien CHANG , Hongzhong ZHENG
CPC classification number: G06F3/0613 , G06F3/0625 , G06F3/0659 , G06F3/0685 , G06F12/0246 , G06F12/1009 , G06F2212/1024 , G06F2212/1028 , G11C8/06 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , Y02D10/13
Abstract: A non-volatile memory comprises an array of a plurality of non-volatile memory cells, a controller coupled to the array, and an evaluator coupled to an output of the array. In a first operational mode, the controller receives a logical address and selects one non-volatile memory cell for access. In a second operational mode, and the controller receives a logical address and selects N non-volatile memory cells for access in which N is an integer greater than 1. If the logical address is for a read access, in the first operational mode the evaluator is disabled and the read-address output of the array corresponds to one selected non-volatile memory cell, and in the second operational mode the evaluator determines an read-address output corresponding to the received logical address based on a read output of the N selected non-volatile memory cells.
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公开(公告)号：US20170192686A1
公开(公告)日：2017-07-06
申请号：US15017391
申请日：2016-02-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dimin NIU , Mu-Tien CHANG , Hongzhong ZHENG
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0631 , G06F3/0641 , G06F3/0644 , G06F3/0685 , G06F12/0246 , G06F2212/1036 , G06F2212/1041 , G06F2212/205 , G06F2212/217 , G06F2212/222 , G06F2212/7208
Abstract: A hybrid module includes one or more memory modules, each of which includes one or more memory devices and a memory controller, one or more storage modules, each of which includes one or more storage devices and a storage controller. A host interface of the hybrid module includes a main controller and provides an interface with the memory controller and the storage controller. A transaction-based memory interface provides an interface between the main controller and a host memory controller.
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公开(公告)号：US20170040050A1
公开(公告)日：2017-02-09
申请号：US15299445
申请日：2016-10-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mu-Tien CHANG , Krishna MALLADI , Dimin NIU , Hongzhong ZHENG
IPC: G11C11/406 , G11C11/4076
CPC classification number: G11C11/40615 , G06F13/1636 , G11C5/04 , G11C11/40618 , G11C11/4076
Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.
Abstract translation: 公开了一种存储器（1205）。 存储器（1205）可以包括三维堆叠存储器架构（1230）中的动态随机存取存储器（DRAM）核心（1210,1215,1220,1225）堆叠。 每个DRAM内核（1210,1215,1220,1225）可以包括用于存储数据的多个存储体（205-1,205-2,205-3,205-4）。 存储器（1205）还可以包括逻辑层（1235），其可以包括将存储器（1205）与处理器（120）连接的接口（1305）。 逻辑层（1235）还可以包括刷新引擎（115），其可用于刷新多个存储体（205-1,205-2,205-3,205-4）中的一个和一个智能刷新组件（ 305），其可以建议刷新引擎（115）哪个存储体使用无序刷新每次刷新刷新。 在刷新时，智能刷新组件（305）可以使用逻辑（415）来识别事务队列（430）中的待处理事务中的最远存储体。
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