公开(公告)号：US20190235788A1

公开(公告)日：2019-08-01

申请号：US15949934

申请日：2018-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  Jae-Gon LEE ,  Indong KIM

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679

Abstract: A method of page size aware scheduling and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of page size aware scheduling are provided. The method includes determining a size of a media page; determining if the media page is open or closed; performing, by a memory controller, a speculative read operation if the media page is determined to be open; and performing, by the memory controller, a regular read operation if the media page is determined to be closed.

公开(公告)号：US20170255575A1

公开(公告)日：2017-09-07

申请号：US15233850

申请日：2016-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/42

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20220229551A1

公开(公告)日：2022-07-21

申请号：US17713228

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20170255383A1

公开(公告)日：2017-09-07

申请号：US15213386

申请日：2016-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C11/406

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C5/04 ,  G11C11/40611 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20240143173A1

公开(公告)日：2024-05-02

申请号：US18408558

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C29/52 ,  G11C5/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20170365305A1

公开(公告)日：2017-12-21

申请号：US15231629

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Craig HANSON ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G11C7/10 ,  G06F1/32

CPC classification number: G11C7/1072 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/04 ,  G11C5/148 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074 ,  G11C2207/2227 ,  Y02D10/14 ,  Y02D50/20

Abstract: A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.

公开(公告)号：US20250036584A1

公开(公告)日：2025-01-30

申请号：US18918046

申请日：2024-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20200218447A1

公开(公告)日：2020-07-09

申请号：US16819032

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20170010817A1

公开(公告)日：2017-01-12

申请号：US15196726

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young LIM ,  Taeksoo KIM ,  Indong KIM ,  Hangu SOHN

IPC: G06F3/06 ,  G11C14/00

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7203 ,  G11C11/005 ,  G11C14/0018 ,  G11C14/0063

Abstract: Electronic devices and memory management methods thereof are provided. Memory management methods may include setting page data of a nonvolatile memory as a read/write mode, copying the page data of the nonvolatile memory to a dynamic random access memory (DRAM) and setting the page data of the DRAM copied from the nonvolatile memory as a read only mode.

Abstract translation: 提供电子设备及其存储器管理方法。 存储器管理方法可以包括将非易失性存储器的页数据设置为读/写模式，将非易失性存储器的页数据复制到动态随机存取存储器（DRAM），并将从非易失性存储器复制的DRAM的页数据设置为 只读模式。