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    Semiconductor package
    33.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11798929B2

    公开(公告)日：2023-10-24

    申请号：US17381985

    申请日：2021-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Cheon Park ,  Dae-Woo Kim ,  Hyuekjae Lee ,  Taehun Kim

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

    CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827

    Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    35.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230113465A1

    公开(公告)日：2023-04-13

    申请号：US17854659

    申请日：2022-06-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minki Kim ,  Seungduk Baek ,  Soojeoung Park ,  Hyuekjae Lee

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00

    Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

    SEMICONDUCTOR PACKAGE
    37.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220165722A1

    公开(公告)日：2022-05-26

    申请号：US17381985

    申请日：2021-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Cheon PARK ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

    Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

    SEMICONDUCTOR PACKAGE
    38.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220139880A1

    公开(公告)日：2022-05-05

    申请号：US17355874

    申请日：2021-06-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuekjae Lee ,  Dae-woo Kim ,  Eunseok Song

    IPC: H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/18

    Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

    Semiconductor package having stacked semiconductor chips
    39.
    发明授权
    Semiconductor package having stacked semiconductor chips 有权

    公开(公告)号：US11244927B2

    公开(公告)日：2022-02-08

    申请号：US16833761

    申请日：2020-03-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuekjae Lee ,  Jihoon Kim ,  Jihwan Suh ,  Soyoun Lee ,  Jiseok Hong ,  Taehun Kim ,  Jihwan Hwang

    IPC: H01L23/16 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

    Abstract: Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.

    Semiconductor packages having improved reliability in bonds between connection conductors and pads
    40.
    发明授权
    Semiconductor packages having improved reliability in bonds between connection conductors and pads 有权

    公开(公告)号：US11158594B2

    公开(公告)日：2021-10-26

    申请号：US17007223

    申请日：2020-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiseok Hong ,  Hyuekjae Lee ,  Jongpa Hong ,  Jihwan Hwang ,  Taehun Kim

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

    Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

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