公开(公告)号：US20180294274A1

公开(公告)日：2018-10-11

申请号：US15696276

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Sunil SHIM ,  Jaeduk LEE ,  Jaehoon JANG ,  Jeehoon HAN

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.

公开(公告)号：US20150325478A1

公开(公告)日：2015-11-12

申请号：US14665141

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun SEONG ,  Jae-Hwang SIM ,  Jeehoon HAN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.

Abstract translation: 制造半导体器件的方法包括在衬底的第一表面上堆叠蚀刻目标层，第一掩模层和第二掩模层。 多个第一间隔线彼此平行地形成，并且形成第二掩模层上的第一间隔垫线。 形成与第二掩模层上的至少第一间隔垫线接触的第三掩模焊盘。 蚀刻第二掩模层和第一掩模层以形成一个或多个第一掩模线，第一掩模预焊垫和第二掩模图案。 分别形成覆盖第一掩模预备焊盘和第一掩模线的侧壁的第二间隔线。 形成第一掩模垫。 蚀刻目标层被蚀刻以形成连接到导线的导电线和导电焊盘。

公开(公告)号：US20240381641A1

公开(公告)日：2024-11-14

申请号：US18435342

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungeun PARK ,  Solmi KWAK ,  Jinhyuk KIM ,  Hyeongjin KIM ,  Jeongyong SUNG ,  Minsoo SHIN ,  Seungjun SHIN ,  Joongshik SHIN ,  Sunghee CHUNG ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: A vertical memory device may include a common source plate on a substrate including a first region and a second region; gate pattern structures on the common source plate and extending from the first region to the second region, wherein the gate pattern structures include gate patterns and first insulation layers, and wherein the adjacent gate pattern structures are spaced apart from each other; first separation patterns filling first openings between the adjacent gate pattern structures on the first region; second separation patterns filling second openings between the adjacent gate pattern structures on the second region, wherein at least one of the second separation patterns is connected to at least one of the first separation patterns, and wherein the second separation pattern has a shape different from a shape of the first separation pattern; and channel structures passing through the gate pattern structures on the first region.

公开(公告)号：US20230061301A1

公开(公告)日：2023-03-02

申请号：US17857273

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdong KIM ,  Seogoo KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes an upper structure on a lower structure. The upper structure includes a stack structure including gate layers, a vertical memory structure penetrating the stack structure, a bit line electrically connected to the vertical memory structure and below the stack structure, and a conductive pattern electrically connected to the vertical memory structure and on the stack structure. The vertical memory structure includes an insulating core region, a first pad pattern electrically connected to the conductive pattern on the insulating core region, a dielectric structure on a side surface of the insulating core region and a side surface of the first pad pattern, and a channel layer. The channel layer includes a first portion contacting the dielectric structure and a second portion extending from the first portion and between a lower surface of the first pad pattern and an upper surface of the insulating core region.

公开(公告)号：US20230054445A1

公开(公告)日：2023-02-23

申请号：US17739845

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Seungyoon KIM ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a stack structure of alternating interlayer insulating layers and gate electrodes, a separation structure vertically penetrating the stack structure and extending in a first direction, to separate the gate electrodes in a second direction, and vertical structures vertically penetrating the stack structure and arranged at a constant pitch. The vertical structures are arranged along array lines sequentially arranged in the second direction away from a side of the separation structure in a plan view. The vertical structures include a channel structure including a channel layer, a contact structure including a metal plug having an upper surface on a level higher than that of an upper surface of the channel structure, and a dummy structure disposed adjacent to the contact structure. The channel structure, the dummy structure, and the contact structure are disposed to be aligned with each other on at least one of the array lines.

公开(公告)号：US20220310639A1

公开(公告)日：2022-09-29

申请号：US17656088

申请日：2022-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： GIYONG CHUNG ,  Seungyoon KIM ,  Jaeryong SIM ,  Jeehoon HAN

IPC: H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/065 ,  H01L23/528

Abstract: A semiconductor device includes a stack structure and an insulation structure that covers the stack structure, a vertical memory structure that penetrates the stack structure, and a separation structure that penetrates the stack structure and has an upper surface located at a higher level than an upper surface of the vertical memory structure. The stack structure includes three gate stack groups stacked in a vertical direction. Each of the three gate stack groups includes gate layers stacked and spaced apart from each other in the vertical direction. At a height level between a lowermost gate layer and an uppermost gate layer, a side surface of the vertical memory structure includes memory side surface slope changing portions, and a side surface of the separation structure includes separation side surface slope changing portions positioned at substantially a same height level as some of the memory side surface slope changing portions.

公开(公告)号：US20220139945A1

公开(公告)日：2022-05-05

申请号：US17357213

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung JUNG ,  Jaebok BAEK ,  Giyong CHUNG ,  Jeehoon HAN

IPC: H01L27/11565 ,  H01L25/18 ,  H01L25/065 ,  H01L27/11582

Abstract: A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

公开(公告)号：US20210384210A1

公开(公告)日：2021-12-09

申请号：US17155225

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyoun JO ,  Kohji KANAMORI ,  Kwangyoung JUNG ,  Jeehoon HAN

IPC: H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519

Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

公开(公告)号：US20210098483A1

公开(公告)日：2021-04-01

申请号：US16890500

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seogoo KANG ,  Daehyun JANG ,  Jaeryong SIM ,  Jongseon AHN ,  Jeehoon HAN

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11548

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

公开(公告)号：US20210066344A1

公开(公告)日：2021-03-04

申请号：US16850244

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON ,  Seungwon LEE ,  Seogoo KANG ,  Juyoung LIM ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/49 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56

Abstract: A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.