公开(公告)号：US20170365327A1

公开(公告)日：2017-12-21

申请号：US15611169

申请日：2017-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung KIM ,  Sungchul PARK ,  Soo-Ho CHA ,  Seongil O ,  Kwangchol CHOE

IPC: G11C11/4091 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C5/04 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/107

Abstract: Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.

公开(公告)号：US20170206028A1

公开(公告)日：2017-07-20

申请号：US15479795

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Chankyung KIM ,  JongpiI SON

IPC: G06F3/06 ,  G06F12/128

CPC classification number: G06F12/0846 ,  G06F11/1064 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0844 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/128 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40607 ,  G11C11/4093 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/32 ,  G11C29/26 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5002 ,  G11C2207/2245

Abstract: A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.

公开(公告)号：US20240419445A1

公开(公告)日：2024-12-19

申请号：US18814125

申请日：2024-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan RO ,  Shinhaeng KANG ,  Seongil O ,  Seungwoo SEO

IPC: G06F9/30 ,  G06F9/50 ,  G06F12/06 ,  G06F13/16 ,  G06F15/78 ,  H03K19/173

Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

公开(公告)号：US20240036820A1

公开(公告)日：2024-02-01

申请号：US18486518

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Seongil O

IPC: G06F7/48 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F7/48 ,  G06F13/16 ,  G11C7/1048 ,  G11C2207/2272

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

公开(公告)号：US11860793B2

公开(公告)日：2024-01-02

申请号：US17526391

申请日：2021-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Won Woo Ro ,  William Jinho Song ,  Jiwon Lee

IPC: G06F12/109

CPC classification number: G06F12/109 ,  G06F2212/651 ,  G06F2212/657

Abstract: A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

公开(公告)号：US20220406369A1

公开(公告)日：2022-12-22

申请号：US17899141

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jaeyoun YOUN ,  Namsung KIM ,  Kyomin SOHN ,  Seongil O ,  Sukhan LEE

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US20220342828A1

公开(公告)日：2022-10-27

申请号：US17526391

申请日：2021-11-15

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Seongil O ,  Won Woo RO ,  William Jinho SONG ,  Jiwon LEE

IPC: G06F12/109

Abstract: A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

公开(公告)号：US20220107803A1

公开(公告)日：2022-04-07

申请号：US17314476

申请日：2021-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan RO ,  Shinhaeng KANG ,  Seongil O ,  Seungwoo SEO

IPC: G06F9/30 ,  G06F9/50 ,  G06F13/16 ,  H03K19/173

Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

公开(公告)号：US20220068366A1

公开(公告)日：2022-03-03

申请号：US17239854

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jaeyoun YOUN ,  Namsung KIM ,  Kyomin SOHN ,  Seongil O ,  Sukhan LEE

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/10

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US20210365203A1

公开(公告)日：2021-11-25

申请号：US17213732

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Jongpil SON ,  Kyomin SOHN

IPC: G06F3/06

Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.