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    Optimized page programming order for non-volatile memory
    34.
    再颁专利
    Optimized page programming order for non-volatile memory 有权
    针对非易失性存储器优化页面编程顺序

    公开(公告)号：USRE45771E1

    公开(公告)日：2015-10-20

    申请号：US14285833

    申请日：2014-05-23

    Applicant: SanDisk Technologies Inc.

    Inventor： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

    IPC: G06F12/00 ,  G11C11/56

    CPC classification number: G11C11/5628 ,  G11C2211/5648

    Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

    Abstract translation: 在非易失性存储系统中的编程数据传输过程中，数据的记录单元从主机传送到诸如存储卡的存储设备。 对于每个记录单元，数据页按照这样的顺序排列，使得在写入时间较少的页面之前提供需要更长时间写入存储器件的存储器阵列的页面。 由于发生更大程度的并行处理，记录单元的整体编程时间减少。 当将编程所需的时间更长的页面编程到存储器阵列时，将编程所需的较少时间的页面传送到存储器件。 编程完成后，存储器信号通知主机传送下一个记录单元。 数据页可以包括下页，中页和上页。

    Write scheme for charge trapping memory
    35.
    发明授权
    Write scheme for charge trapping memory 有权
    电荷捕获存储器的写入方案

    公开(公告)号：US09093158B2

    公开(公告)日：2015-07-28

    申请号：US14099130

    申请日：2013-12-06

    Applicant: SanDisk Technologies Inc.

    Inventor： Deepak Raghu ,  Chris Avila ,  Gautam A. Dusija ,  Yingda Dong

    IPC: G11C16/00 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/22 ,  G11C16/3427

    Abstract: In a charge trapping memory, data that would otherwise be likely to remain adjacent to unwritten word lines is written three times, along three immediately adjacent word lines. The middle copy is protected from charge migration on either side and is considered a safe copy for later reading. Dummy data may be programmed along a number of word lines to format a block for good data retention.

    Abstract translation: 在电荷捕获存储器中，否则可能保持与未写入字线相邻的数据将沿着三个紧邻的字线被写入三次。 中间副本在任何一方都受到保护，免受电费迁移，并被视为安全副本供以后阅读。 可以沿着多个字线编程虚拟数据以格式化块以获得良好的数据保留。

    WRITE SCHEME FOR CHARGE TRAPPING MEMORY
    37.
    发明申请
    WRITE SCHEME FOR CHARGE TRAPPING MEMORY 有权
    写入存储器的写入方案

    公开(公告)号：US20150162087A1

    公开(公告)日：2015-06-11

    申请号：US14099130

    申请日：2013-12-06

    Applicant: SanDisk Technologies Inc.

    Inventor： Deepak Raghu ,  Chris Avila ,  Gautam A. Dusija ,  Yingda Dong

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/22 ,  G11C16/3427

    Abstract: In a charge trapping memory, data that would otherwise be likely to remain adjacent to unwritten word lines is written three times, along three immediately adjacent word lines. The middle copy is protected from charge migration on either side and is considered a safe copy for later reading. Dummy data may be programmed along a number of word lines to format a block for good data retention.

    Abstract translation: 在电荷俘获存储器中，否则可能保持与未写入字线相邻的数据将沿着三个紧邻的字线被写入三次。 中间副本在任何一方都受到保护，免受电费迁移，并被视为安全副本供以后阅读。 可以沿着多个字线编程虚拟数据以格式化块以获得良好的数据保留。

    Detecting Programmed Word Lines Based On NAND String Current
    39.
    发明申请
    Detecting Programmed Word Lines Based On NAND String Current 有权

    公开(公告)号：US20150124527A1

    公开(公告)日：2015-05-07

    申请号：US14594473

    申请日：2015-01-12

    Applicant: SanDisk Technologies Inc.

    Inventor： Man L Mui ,  Yingda Dong ,  Chris Avila

    IPC: G11C16/34

    CPC classification number: G11C16/3459 ,  G11C11/5635 ,  G11C11/5642 ,  G11C13/004 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3454

    Abstract: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.

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