公开(公告)号：US20220059157A1

公开(公告)日：2022-02-24

申请号：US16996412

申请日：2020-08-18

Applicant: SanDisk Technologies LLC

Inventor： Zhixin Cui ,  Rajdeep Gautam ,  Hardwell Chibvongodze

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/02

Abstract: Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation,

公开(公告)号：US11114462B1

公开(公告)日：2021-09-07

申请号：US16794563

申请日：2020-02-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Ippei Yasuda

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

公开(公告)号：US11069703B2

公开(公告)日：2021-07-20

申请号：US16291504

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio Nishida ,  Mitsuteru Mushiga ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L25/065 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

公开(公告)号：US11024635B2

公开(公告)日：2021-06-01

申请号：US16879903

申请日：2020-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Yanli Zhang

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11575 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11519

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

公开(公告)号：US20200286915A1

公开(公告)日：2020-09-10

申请号：US16878865

申请日：2020-05-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Yanli Zhang

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11529 ,  H01L27/1157 ,  H01L21/764 ,  H01L29/06

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

公开(公告)号：US10707233B1

公开(公告)日：2020-07-07

申请号：US16362857

申请日：2019-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L21/3105 ,  H01L27/1157 ,  H01L27/11524 ,  H01L23/528 ,  H01L23/532 ,  H01L29/08 ,  H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

公开(公告)号：US10586803B2

公开(公告)日：2020-03-10

申请号：US16023289

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura ,  Zhixin Cui ,  Kiyohiko Sakakibara

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11519

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US10580783B2

公开(公告)日：2020-03-03

申请号：US15909073

申请日：2018-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hiroshi Minakata ,  Keigo Kitazawa ,  Yoshiyuki Okura

IPC: H01L27/11556 ,  H01L27/11529 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/788

Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.

公开(公告)号：US10192784B1

公开(公告)日：2019-01-29

申请号：US15902169

申请日：2018-02-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hiroshi Minakata ,  Keigo Kitazawa ,  Yoshiyuki Okura

IPC: H01L27/11524 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: An alternating stack of insulating layers and sacrificial material layers including stepped surfaces is formed over a substrate. After formation of a retro-stepped dielectric material portion over the stepped surfaces, an array of cylindrical openings is formed through the retro-stepped dielectric material portion and the alternating stack. A continuous cavity is formed by isotropically etching the insulating layers and the retro-stepped dielectric material portion selective to the sacrificial material layers. Remaining portions of the retro-stepped dielectric material portion include dielectric pillar structures. A continuous fill material portion is formed in the continuous cavity. Memory stack structures are formed through the alternating stack. The sacrificial material layers and the dielectric pillar structures are replaced with combinations of an electrically conductive layer and a contact via structure. The contact via structures are self-aligned to the electrically conductive layers.

公开(公告)号：US12284807B2

公开(公告)日：2025-04-22

申请号：US17397777

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.