公开(公告)号：US20130095623A1

公开(公告)日：2013-04-18

申请号：US13611113

申请日：2012-09-12

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

摘要： A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

公开(公告)号：US20130087759A1

公开(公告)日：2013-04-11

申请号：US13270362

申请日：2011-10-11

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/06 ,  H01L33/00 ,  B82Y99/00

CPC分类号： H01L33/0041 ,  H01L33/26 ,  H01L33/34 ,  H01L33/40 ,  H01L51/0048 ,  H01L51/5203 ,  H01L51/5296

摘要： Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

公开(公告)号：US08367508B2

公开(公告)日：2013-02-05

申请号：US12757201

申请日：2010-04-09

申请人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76897 ,  H01L21/78 ,  H01L29/66545

摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.

摘要翻译： 一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅， 漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除 暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。

公开(公告)号：US20120061772A1

公开(公告)日：2012-03-15

申请号：US12880085

申请日：2010-09-11

申请人： Dechao Guo ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/28079 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42372 ,  H01L29/517 ,  H01L29/66545

摘要： A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

摘要翻译： 通过在衬底的掺杂区域上去除多晶硅栅极并在衬底上形成掩模层来制造晶体管，使得掺杂区域通过掩模层内的孔露出。 界面层沉积在掩模层的顶表面和侧表面上以及在掺杂区的顶表面上。 适于降低晶体管的阈值电压和/或降低晶体管的反型层的厚度的层被沉积在界面层上。 该层包括扩散到界面层中的金属，例如铝或镧，并且还包括氧化物，例如氧化铪。 在掩模层的孔内形成导电塞，例如金属塞。 界面层，界面层上的层和导电插塞是晶体管的替代栅极。

公开(公告)号：US08519454B2

公开(公告)日：2013-08-27

申请号：US13075443

申请日：2011-03-30

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/76 ,  H01L21/338 ,  H01L21/84

CPC分类号： H01L29/4966 ,  H01L29/66545 ,  H01L29/7843

摘要： Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.

摘要翻译： 本文提供了用于替换金属栅极集成方案和所得器件的金属填充工艺。 该方法包括在半导体衬底上形成虚拟栅极。 虚拟门包括在第一材料和第二材料之间形成金属层。 该方法还包括部分地去除伪栅极以形成由间隔物材料限定的开口。 该方法还包括在间隔物材料中形成凹槽以加宽开口的一部分。 该方法还包括通过开口去除虚拟栅极的剩余部分以形成具有形成其上部的凹部的沟槽。 该方法还包括用替换的金属栅极堆叠填充沟槽和凹部。

公开(公告)号：US20120299118A1

公开(公告)日：2012-11-29

申请号：US13560240

申请日：2012-07-27

申请人： Dechao Guo ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Keith Kwong Hon Wong

IPC分类号： H01L27/088

CPC分类号： H01L29/78696 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795

摘要： A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel.

摘要翻译： 场效应晶体管器件包括设置在衬底上的第一导电沟道，设置在衬底上的第二导电沟道，形成在第一导电沟道上的第一栅极叠层，第一栅叠层包括具有第一氧含量的金属层， 形成在第二导电沟道上的第二栅极堆叠a，第二栅极堆叠包括具有第二氧的金属层，连接到第一导电沟道和第二导电沟道的离子掺杂源区，以及连接到第二导电沟的离子掺杂漏极区 第一导电沟道和第二导电沟道。

公开(公告)号：US20110248321A1

公开(公告)日：2011-10-13

申请号：US12757201

申请日：2010-04-09

申请人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76897 ,  H01L21/78 ,  H01L29/66545

摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.

摘要翻译： 一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅， 漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除 暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。

公开(公告)号：US20110095379A1

公开(公告)日：2011-04-28

申请号：US12607110

申请日：2009-10-28

申请人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

公开(公告)号：US08772149B2

公开(公告)日：2014-07-08

申请号：US13276395

申请日：2011-10-19

申请人： Eduard A. Cartier ,  Brian J. Greene ,  Dechao Guo ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong

发明人： Eduard A. Cartier ,  Brian J. Greene ,  Dechao Guo ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/785 ,  H01L21/02323 ,  H01L21/28017 ,  H01L27/1211 ,  H01L29/6656 ,  H01L29/66795

摘要： FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

摘要翻译： 公开了FinFET结构和制造FinFET结构的方法。 该方法包括在FinFET结构的栅极堆叠上执行氧退火处理以引起Vt偏移。 氧退火工艺在侧壁下拉和硅化后进行。

公开(公告)号：US08680646B2

公开(公告)日：2014-03-25

申请号：US13605529

申请日：2012-09-06

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/00

CPC分类号： H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

摘要： A device and method for device fabrication include forming a buried gate electrode in a dielectric substrate and patterning a stack having a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

摘要翻译： 用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅极电极，并且在掩埋栅电极上图案化具有高介电常数层，碳基半导电层和保护层的叠层。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。