公开(公告)号：US20130020548A1

公开(公告)日：2013-01-24

申请号：US13189401

申请日：2011-07-22

申请人： Mark Harold CLARK ,  Scott Brad Herner

发明人： Mark Harold CLARK ,  Scott Brad Herner

IPC分类号： H01L45/00 ,  H01L21/20 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L27/2463 ,  H01L21/02532 ,  H01L21/0262 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1675

摘要： A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.

摘要翻译： 一种形成非易失性存储器件的方法包括提供具有表面的衬底，沉积覆盖在表面上的电介质，形成覆盖电介质的第一布线结构，沉积覆盖第一布线结构的硅材料，硅层的厚度 小于约100埃，使用硅层作为种子层，以大约400至大约490摄氏度的温度沉积硅锗材料，其中硅锗材料基本上没有空隙并具有多晶特性 沉积覆盖硅锗材料的电阻开关材料（例如非晶硅材料），沉积覆盖电阻材料的导电材料，以及形成覆盖导电材料的第二布线结构。

公开(公告)号：US08330250B2

公开(公告)日：2012-12-11

申请号：US13229747

申请日：2011-09-11

申请人： Scott Brad Herner

发明人： Scott Brad Herner

IPC分类号： H01L29/00

CPC分类号： H01L27/06 ,  G11C13/0069 ,  G11C17/16 ,  G11C2013/009 ,  G11C2213/33 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/91 ,  H01L2924/00

摘要： A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided.

摘要翻译： 提供了一种垂直取向的p-i-n二极管，其包括在硅化物，锗化物或硅化物 - 锗化物层附近结晶的半导体材料，以及与二极管串联设置的电介质材料。 电介质材料的介电常数大于8，并且与第一金属层和第二金属层相邻。 提供了许多其他方面。

公开(公告)号：US08252644B2

公开(公告)日：2012-08-28

申请号：US13228109

申请日：2011-09-08

申请人： Scott Brad Herner ,  Steven J. Radigan

发明人： Scott Brad Herner ,  Steven J. Radigan

IPC分类号： H01L29/80

CPC分类号： G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/1021 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/868

摘要： A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF2 ions. Numerous additional aspects are provided.

摘要翻译： 提供了一种用于形成非易失性存储单元的方法，其包括：（1）在基板上形成轨道状的第一导体，（2）在第一导体的上方形成轨道状的第二导体，以及（3） 第一支柱设置在第一导体和第二导体之间。 第一柱包括垂直定向的pin二极管，并且pin二极管包括：（a）具有第一导电类型的底部重掺杂区域，（b）中间固有或轻掺杂区域，以及（c）顶部重掺杂区域 具有与第一导电类型相反的第二导电类型。 通过注入砷离子来掺杂底部重掺杂区，通过注入BF 2离子来掺杂顶部重掺杂区。 还提供了许多其他方面。

公开(公告)号：US07678420B2

公开(公告)日：2010-03-16

申请号：US11159031

申请日：2005-06-22

申请人： Scott Brad Herner

发明人： Scott Brad Herner

IPC分类号： C23C16/00 ,  C23C16/22

CPC分类号： C23C16/0272 ,  C23C16/28

摘要： A chemical vapor deposition method provides a smooth continuous germanium film layer, which is deposited on a metallic substrate at a sufficiently lower temperature to provide a germanium device suitable for use with temperature sensitive materials such as aluminum and copper. Another chemical vapor deposition method provides a smooth continuous silicon germanium film layer, which is deposited on a silicon dioxide substrate at a sufficiently low temperature to provide a germanium device suitable for use with temperature sensitive materials such as aluminum, copper and chalcogenides memory materials.

摘要翻译： 化学气相沉积方法提供光滑的连续锗膜层，其在足够低的温度下沉积在金属基底上，以提供适用于温度敏感材料如铝和铜的锗装置。 另一种化学气相沉积方法提供平滑的连续硅锗膜层，其在足够低的温度下沉积在二氧化硅衬底上，以提供适用于温度敏感材料如铝，铜和硫族化物记忆材料的锗装置。

公开(公告)号：US07144807B2

公开(公告)日：2006-12-05

申请号：US10247071

申请日：2002-09-18

申请人： Scott Brad Herner ,  Michael A. Vyvoda

发明人： Scott Brad Herner ,  Michael A. Vyvoda

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L23/53209 ,  H01L21/76889 ,  H01L2924/0002 ,  H01L2924/00

摘要： Low resistivity, C54-phase TiSi2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about 2.4 times the thickness of the subsequently deposited Ti film. Upon thermal annealing above 750° C., the undoped amorphous Si is consumed by the reaction of Ti+Si to form TiSi2, forming a low-resistivity, C54-phase TiSi2 film on top of heavily doped polysilicon. The annealing temperature required to form C54 phase TiSi2 is reduced by consuming undoped amorphous Si in the reaction of Ti and Si, as compared with heavily doped polysilicon. Narrow lines (

公开(公告)号：US11018122B1

公开(公告)日：2021-05-25

申请号：US16671075

申请日：2019-10-31

申请人： Scott Brad Herner

发明人： Scott Brad Herner

IPC分类号： H01L25/16 ,  H01L27/12

摘要： This application describes a subpixel apparatus comprising two transistors, a capacitor, and a small LED. The transistors and capacitor are fabricated in such a manner as to occupy a reduced area and have the small LED overlie them. Methods to form the subpixel apparatus are discussed.

公开(公告)号：US09087576B1

公开(公告)日：2015-07-21

申请号：US13434567

申请日：2012-03-29

申请人： Scott Brad Herner

发明人： Scott Brad Herner

IPC分类号： H01L29/02 ,  G11C13/00 ,  H01L27/102

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/1021 ,  H01L27/224

摘要： A non-volatile memory device structure. The device structure includes a first electrode, a second electrode and a state change material sandwiched between the first electrode and the second electrode. In a specific embodiment, the first electrode includes a p+ type polycrystalline silicon material or a p+ type silicon germanium material. The state change material includes an n− type zinc oxide material. The second electrode includes a doped zinc oxide material. The doped zinc oxide material can be B2O3:ZnO, In2O3:ZnO, Al2O3:ZnO or Ga2O3:ZnO. The n− type zinc oxide material and the p+ type silicon material (or p+ polycrystalline silicon germanium material) further form a diode device or steering device for the non-volatile memory device.

摘要翻译： 非易失性存储器件结构。 器件结构包括夹在第一电极和第二电极之间的第一电极，第二电极和状态变化材料。 在具体实施例中，第一电极包括p +型多晶硅材料或p +型硅锗材料。 状态变化材料包括n-型氧化锌材料。 第二电极包括掺杂的氧化锌材料。 掺杂的氧化锌材料可以是B2O3：ZnO，In2O3：ZnO，Al2O3：ZnO或Ga2O3：ZnO。 n型氧化锌材料和p +型硅材料（或p +多晶硅锗材料）还形成用于非易失性存储器件的二极管器件或转向器件。

公开(公告)号：US09012307B2

公开(公告)日：2015-04-21

申请号：US12835704

申请日：2010-07-13

申请人： Sung Hyun Jo ,  Scott Brad Herner

发明人： Sung Hyun Jo ,  Scott Brad Herner

IPC分类号： H01L21/82 ,  H01L21/20 ,  H01L45/00

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/143 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

摘要： A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process.

摘要翻译： 一种形成两个终端设备的方法。 该方法包括形成覆盖在衬底的表面区域上的第一电介质材料。 底部布线材料形成在第一介电材料上方，并且覆盖在底部布线材料上的开关材料沉积。 对底部布线材料和开关材料进行第一图案化和蚀刻工艺以形成具有顶表面区域和侧面区域的第一结构。 第一结构至少包括底部布线结构和具有第一侧面区域的开关元件和包括开关元件的暴露区域的顶表面区域。 至少形成包括开关元件的暴露区域的第一结构的第二电介质材料。 该方法在第二电介质层的一部分中形成开口区域，以露出开关元件的顶表面区域的一部分。 包括导电材料的顶部布线材料形成为覆盖开口区域，使得导电材料与开关元件直接接触。 执行第二蚀刻工艺以形成至少顶部布线结构。 在具体实施例中，包括开关元件的第一侧区域的第一结构的侧面区域没有来自第二蚀刻工艺的污染物导电材料。

公开(公告)号：US08399307B2

公开(公告)日：2013-03-19

申请号：US13532019

申请日：2012-06-25

申请人： Scott Brad Herner

发明人： Scott Brad Herner

IPC分类号： H01L21/82

CPC分类号： H01L21/76895 ,  H01L23/5226 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.

摘要翻译： 一种形成存储器件的方法包括：提供具有表面区域，限定单元区域和第一和第二外围区域的衬底，顺序形成第一电介质材料，用于第一阵列器件的第一布线结构和第二电介质材料 在所述表面区域上形成在所述第一周边区域中的开口区域，所述开口区域在至少所述第一和第二电介质材料的一部分中延伸以暴露所述第一布线结构和所述基板的部分，形成第二布线材料， 覆盖所述第二电介质材料并填充所述开口区域以在所述第一周边区域中形成垂直互连结构，以及从所述第二布线材料形成用于第二阵列器件的第二布线结构，所述第一和第二布线结构与每个 另一个并通过垂直互连结构电连接。

公开(公告)号：US08394670B2

公开(公告)日：2013-03-12

申请号：US13149807

申请日：2011-05-31

申请人： Scott Brad Herner

发明人： Scott Brad Herner

IPC分类号： H01L29/02 ,  H01L45/00

CPC分类号： H01L43/08 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/16 ,  H01L29/24 ,  H01L29/267 ,  H01L29/8615

摘要： A steering device. The steering device includes an n-type impurity region comprising a zinc oxide material and a p-type impurity region comprising a silicon germanium material. A pn junction region formed from the zinc oxide material and the silicon germanium material. The steering device is a serially coupled to a resistive switching device to provide rectification for the resistive switching device to form a non-volatile memory device.