公开(公告)号：US10586505B2

公开(公告)日：2020-03-10

申请号：US16199336

申请日：2018-11-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hajime Kimura

IPC: G09G3/36 ,  G11C19/28 ,  H01L27/088 ,  G02F1/133 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

公开(公告)号：US10312267B2

公开(公告)日：2019-06-04

申请号：US16004882

申请日：2018-06-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki ,  Shunpei Yamazaki

IPC: H01L29/12 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1334 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36 ,  H01L29/24 ,  H01L21/8234

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

公开(公告)号：US10311960B2

公开(公告)日：2019-06-04

申请号：US15584117

申请日：2017-05-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/18 ,  G09G3/36 ,  G09G3/3266

Abstract: The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire.

公开(公告)号：US10269833B2

公开(公告)日：2019-04-23

申请号：US15810228

申请日：2017-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/786 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/417 ,  H01L29/423 ,  G11C19/28 ,  G02F1/1333 ,  G02F1/1343 ,  G09G3/36

Abstract: A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

公开(公告)号：US10199006B2

公开(公告)日：2019-02-05

申请号：US14680520

申请日：2015-04-07

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Atsushi Umezaki

IPC: H03K5/15 ,  G11C19/28 ,  G09G3/20 ,  G09G3/36 ,  H03K3/356 ,  H03K4/00 ,  G09G5/00 ,  H03K4/02

Abstract: A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to third transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

公开(公告)号：US20190033675A1

公开(公告)日：2019-01-31

申请号：US16143059

申请日：2018-09-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G02F1/1362 ,  G02F1/133 ,  H01L29/786 ,  G02F1/1368 ,  G11C19/28 ,  H01L29/24 ,  H01L27/06 ,  G09G3/34 ,  H01L27/12 ,  G09G3/36 ,  H01L27/15 ,  G02F1/1345 ,  G02F1/1335 ,  G02F1/139 ,  G02F1/1337 ,  H01L21/67 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

CPC classification number: G02F1/136286 ,  G02F1/13306 ,  G02F1/133753 ,  G02F1/13452 ,  G02F1/136213 ,  G02F1/1368 ,  G02F1/1393 ,  G02F2001/133622 ,  G02F2202/103 ,  G09G3/342 ,  G09G3/3655 ,  G09G3/3674 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/024 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2330/021 ,  G11C19/28 ,  H01L21/67167 ,  H01L27/06 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/15 ,  H01L27/156 ,  H01L27/3211 ,  H01L27/3213 ,  H01L27/3216 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/247 ,  H01L29/78693 ,  H01L51/5246 ,  H01L51/56 ,  H01L2251/5307 ,  H01L2251/5315 ,  H01L2251/5323

Abstract: A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

公开(公告)号：US10068927B2

公开(公告)日：2018-09-04

申请号：US14886335

申请日：2015-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H03B5/36 ,  G09G3/34 ,  G09G3/32 ,  G09G3/20 ,  B81B3/00 ,  G02B26/02 ,  G02B26/00 ,  H01L27/12

Abstract: A semiconductor device includes a MEMS device, a first transistor that supplies a first voltage to a first electrode of the MEMS device, a second transistor that supplies a second voltage to the first electrode of the MEMS device, a third transistor that supplies a first video signal to a gate of the first transistor, a fourth transistor that supplies the first voltage to a second electrode of the MEMS device, a fifth transistor that supplies the second voltage to the second electrode of the MEMS device, and a sixth transistor that supplies a second video signal to a gate of the fourth transistor. A gate of the second transistor is connected to the gate of the fourth transistor. A gate of the fifth transistor is connected to the gate of the first transistor.

公开(公告)号：US10026848B2

公开(公告)日：2018-07-17

申请号：US15168293

申请日：2016-05-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G5/00 ,  H01L29/786 ,  G09G3/20 ,  G09G3/36 ,  G11C19/28 ,  H01L21/477 ,  H01L27/12

Abstract: One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

公开(公告)号：US09941308B2

公开(公告)日：2018-04-10

申请号：US15145908

申请日：2016-05-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G02F1/136 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1343 ,  G09G3/3266 ,  G09G3/34 ,  G09G3/36 ,  G11C19/28 ,  H01L27/06 ,  H01L27/32 ,  H01L29/786 ,  G02F1/1368

CPC classification number: H01L27/1255 ,  G02F1/134309 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3266 ,  G09G3/3413 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2310/0235 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/0629 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/78663 ,  H01L29/78672 ,  H01L29/7869

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

公开(公告)号：US09806107B2

公开(公告)日：2017-10-31

申请号：US15247995

申请日：2016-08-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H03B1/00 ,  H03K3/00 ,  H01L27/12 ,  H01L29/786 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  H03K17/687 ,  G11C19/00

CPC classification number: H01L27/1255 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00 ,  H01L29/7869 ,  H03B1/00 ,  H03K3/00 ,  H03K17/6871

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.