公开(公告)号：US10424676B2

公开(公告)日：2019-09-24

申请号：US16214197

申请日：2018-12-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Satoru Okamoto ,  Shunpei Yamazaki

IPC: H01L21/311 ,  H01L21/3213 ,  H01L29/786

Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.

公开(公告)号：US09773919B2

公开(公告)日：2017-09-26

申请号：US15235242

申请日：2016-08-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Takashi Hamada ,  Akihisa Shimomura ,  Satoru Okamoto ,  Katsuaki Tochibayashi

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/465 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

公开(公告)号：US11626422B2

公开(公告)日：2023-04-11

申请号：US17319389

申请日：2021-05-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/24 ,  H01L29/51

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US11489065B2

公开(公告)日：2022-11-01

申请号：US17073639

申请日：2020-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru Okamoto ,  Shinya Sasagawa

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/385 ,  H01L29/22 ,  H01L29/24 ,  H01L29/40

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

公开(公告)号：US11245040B2

公开(公告)日：2022-02-08

申请号：US16970567

申请日：2019-02-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Katsuaki Tochibayashi ,  Satoru Okamoto

IPC: H01L29/786 ,  H01L29/22 ,  H01L29/51

Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a first conductor and a second conductor that are apart from each other over the first oxide; a second insulator covering the first insulator, the first oxide, the first conductor, and the second conductor; a third insulator over the second insulator; a fourth insulator in contact with a first conductor, a side surface of the second conductor, a side surface of the second insulator, and a side surface of the third insulator; a fifth insulator that is over the first oxide and on an inner side of the fourth insulator; a third conductor on an inner side of the fifth insulator; and a sixth insulator that is in contact with a top surface of the fourth insulator and over the third insulator, the fifth insulator, and the third conductor. The fourth insulator is divided to be apart from each other over the first oxide.

公开(公告)号：US11101386B2

公开(公告)日：2021-08-24

申请号：US16634493

申请日：2018-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Ryota Hodo ,  Daigo Ito ,  Hiroaki Honda ,  Satoru Okamoto

IPC: H01L29/786 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/105 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/24 ,  H01L29/417

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor. The first insulator is between the third insulator and the third conductor, and between the fourth insulator and the third conductor.

公开(公告)号：US11024743B2

公开(公告)日：2021-06-01

申请号：US16378622

申请日：2019-04-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshinobu Asami ,  Yutaka Okazaki ,  Satoru Okamoto ,  Shinya Sasagawa

IPC: H01L29/786 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L21/475 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/67 ,  C23C16/40 ,  C23C16/455 ,  H01L27/12

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

公开(公告)号：US10665613B2

公开(公告)日：2020-05-26

申请号：US16280792

申请日：2019-02-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota Hodo ,  Motomu Kurata ,  Shinya Sasagawa ,  Satoru Okamoto ,  Shunpei Yamazaki

IPC: H01L23/532 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/467 ,  H01L21/463 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L29/778

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

公开(公告)号：US10367015B2

公开(公告)日：2019-07-30

申请号：US15298307

申请日：2016-10-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru Okamoto ,  Shunpei Yamazaki

IPC: H01L27/12 ,  H01L27/105 ,  H01L27/146 ,  H01L29/786

Abstract: Provided is a semiconductor device which can reduce leakage of current between wirings. Included steps are forming a first insulator over a first conductor which is formed over substrate; forming a first hard mask thereover; forming a first resist mask comprising a first opening, over the first hard mask; etching the first hard mask to form a second hard mask comprising a second opening; etching the first insulator using the second hard mask to form a second insulator comprising a third opening; forming a second conductor embedded in the second opening and the third opening; performing polishing treatment on the second hard mask and the second conductor to form a third conductor embedded in the third opening; forming a fourth conductor thereover; forming a second resist mask in a pattern over the fourth conductor; and dry-etching the fourth conductor to form a fifth conductor. The second hard mask can be dry-etched.

公开(公告)号：US10256348B2

公开(公告)日：2019-04-09

申请号：US15903097

申请日：2018-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Satoru Okamoto

IPC: H01L29/40 ,  H01L29/786 ,  H01L27/12 ,  H01L27/146 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.