公开(公告)号：US20120242627A1

公开(公告)日：2012-09-27

申请号：US13052446

申请日：2011-03-21

申请人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

发明人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

IPC分类号： G06F3/038 ,  H01L29/24 ,  H01L29/04 ,  H01L21/385

CPC分类号： H01L29/66742 ,  G02B26/001 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78693

摘要： This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

摘要翻译： 本公开提供了用于制造薄膜晶体管器件的系统，方法和装置。 一方面，提供了在源极区域和漏极区域之间具有源极区域，漏极区域和沟道区域的衬底。 衬底还包括氧化物半导体层，覆盖沟道区的第一介电层和介电层上的第一金属层。 在覆盖源极区域和漏极区域的氧化物半导体层上形成第二金属层。 处理氧化物半导体层和第二金属层以在覆盖源极区和漏极区的氧化物半导体层中形成重掺杂的n型氧化物半导体。 也可以形成第二金属层中的氧化物。

公开(公告)号：US07569503B2

公开(公告)日：2009-08-04

申请号：US11271488

申请日：2005-11-10

申请人： Yaoling Pan ,  David P. Stumbo

发明人： Yaoling Pan ,  David P. Stumbo

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7606 ,  H01L29/78696 ,  Y10S977/901 ,  Y10S977/963

摘要： Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm2 (e.g., less than about 50 mJ/cm2, e.g., between about 2 and 18 mJ/cm2) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.

摘要翻译： 提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。 在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。 根据本发明的另外的实施例，使用使用低于约100mJ / cm 2（例如，小于约50mJ / cm 2，例如约2至18mJ / cm 2）的相对低的激​​光能量密度的激光能量的脉冲激光退火 以在基底上退火纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。

公开(公告)号：US07786024B2

公开(公告)日：2010-08-31

申请号：US11936590

申请日：2007-11-07

申请人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

发明人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B23K26/073 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the nanowires to anneal at least a portion of the nanowires. The nanowires may be aligned substantially parallel to an axis. The laser beam may be polarized in various ways to modify absorption of radiation of the applied laser beam by the nanowires. For example, the laser beam may be polarized in a direction substantially parallel to the axis or substantially perpendicular to the axis to enable different nanowire absorption profiles.

摘要翻译： 提供了用于退火半导体纳米线并用于制造电气器件的方法，系统和装置。 纳米线沉积在基底上。 形成多个电极。 纳米线与多个电极电接触。 纳米线是掺杂的。 将极化激光束施加到纳米线以退火至少一部分纳米线。 纳米线可以基本上平行于轴线对准。 激光束可以以各种方式被极化，以通过纳米线来改变施加的激光束的辐射的吸收。 例如，激光束可以在基本上平行于轴线或基本上垂直于轴线的方向上极化，以实现不同的纳米线吸收曲线。

公开(公告)号：US06678435B2

公开(公告)日：2004-01-13

申请号：US09861120

申请日：2001-05-18

申请人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

发明人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

IPC分类号： G02B626

CPC分类号： G02B6/3576 ,  G02B6/3538 ,  G02B6/3546 ,  G02B2006/12145

摘要： An optical switch having an insulator under a heater element is disclosed. The insulator reduces the heat loss thereby making the switch more efficient. The insulator is fabricated embedded in the underlying substrate on which the heater and the optical intersection are fabricated. A method of fabricating the optical switch having an insulator is disclosed. A trench is etched on the substrate and filled with oxide or other suitable insulating material. Then, the heater and the optical intersection are fabricated above the insulator.

摘要翻译： 公开了一种在加热器元件下方具有绝缘体的光开关。 绝缘体减少热损失，从而使开关更有效率。 制造的绝缘体嵌入在其上制造加热器和光学交叉点的下面的基板上。 公开了一种制造具有绝缘体的光开关的方法。 在衬底上蚀刻沟槽，并填充有氧化物或其它合适的绝缘材料。 然后，在绝缘体上方制造加热器和光学交叉点。

公开(公告)号：US06423939B1

公开(公告)日：2002-07-23

申请号：US09678288

申请日：2000-10-02

申请人： Yaoling Pan

发明人： Yaoling Pan

IPC分类号： H05B100

CPC分类号： H01L24/81 ,  H01L23/345 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/98 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13111 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0212 ,  H05K1/167 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/10674 ,  H05K2203/1115 ,  H01L2224/05552 ,  H01L2924/00

摘要： An apparatus having a heating circuit including a resistor layer and a patterned conductor layer is disclosed. The pattern defines a current path that includes at least one portion of the resistor layer. When current is applied to the current path, heat is generated in the portion of the resistor layer that is a part of the current path. The heat is used to reflow solder to connect two components such as an integrated circuit chip (IC) to a multi-chip module (MCM) module. This localized electric heating method may be used to package multiple chips on a module. The apparatus having the heating circuit may be fabricated by first depositing a resistor layer on to a substrate. Then, a conductor layer is deposited and etched to define the current path.

摘要翻译： 公开了一种具有包括电阻层和图案化导体层的加热电路的装置。 该图案定义了包括电阻层的至少一部分的电流路径。 当电流施加到电流路径时，在作为电流路径的一部分的电阻层的部分产生热量。 热量用于回流焊接以将诸如集成电路芯片（IC）的两个组件连接到多芯片模块（MCM）模块。 该局部电加热方法可用于在模块上封装多个芯片。 具有加热电路的装置可以通过首先在基板上沉积电阻层来制造。 然后，沉积并蚀刻导体层以限定电流路径。

公开(公告)号：US08817358B2

公开(公告)日：2014-08-26

申请号：US13565688

申请日：2012-08-02

申请人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

发明人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

IPC分类号： G02B26/00 ,  G02F1/03

CPC分类号： G02B26/001

摘要： This disclosure provides systems, methods and apparatus for a thin film stack with surface-conditioning buffer layers. In one aspect, the thin film stack includes a plurality of thin film layers each having a thickness greater than about 10 nm and a plurality of surface-conditioning buffer layers each having a thickness between about 1 nm and about 10 nm. The surface-conditioning buffer layers are alternatingly disposed between the thin film layers. Each of the surface-conditioning buffer layers are formed with the same or substantially the same thickness and composition. In some implementations, the surface-conditioning buffer layers are formed by atomic layer deposition.

摘要翻译： 本公开提供了具有表面调节缓冲层的薄膜堆叠的系统，方法和装置。 在一个方面，薄膜堆叠包括多个厚度大于约10nm的薄膜层以及各自具有约1nm至约10nm厚度的多个表面调节缓冲层。 表面调节缓冲层交替地设置在薄膜层之间。 每个表面调节缓冲层以相同或基本上相同的厚度和组成形成。 在一些实施方案中，表面调节缓冲层通过原子层沉积形成。

公开(公告)号：US08797303B2

公开(公告)日：2014-08-05

申请号：US13052446

申请日：2011-03-21

申请人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

发明人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

IPC分类号： G09G5/00 ,  H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  G02B26/00

CPC分类号： H01L29/66742 ,  G02B26/001 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78693

摘要： This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

摘要翻译： 本公开提供了用于制造薄膜晶体管器件的系统，方法和装置。 一方面，提供了在源极区域和漏极区域之间具有源极区域，漏极区域和沟道区域的衬底。 衬底还包括氧化物半导体层，覆盖沟道区的第一介电层和介电层上的第一金属层。 在覆盖源极区域和漏极区域的氧化物半导体层上形成第二金属层。 处理氧化物半导体层和第二金属层以在覆盖源极区和漏极区的氧化物半导体层中形成重掺杂的n型氧化物半导体。 也可以形成第二金属层中的氧化物。

公开(公告)号：US20060234519A1

公开(公告)日：2006-10-19

申请号：US11271488

申请日：2005-11-10

申请人： Yaoling Pan ,  David Stumbo

发明人： Yaoling Pan ,  David Stumbo

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7606 ,  H01L29/78696 ,  Y10S977/901 ,  Y10S977/963

摘要： Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm2 (e.g., less than about 50 mJ/cm2, e.g., between about 2 and 18 mJ/cm2) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.

摘要翻译： 提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。 在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。 根据本发明的另外的实施例，使用在低于约100mJ / cm 2（例如小于约50mJ / cm 2）的较低激光能量密度的激光能量进行脉冲激光退火， SUP>，例如约2和18mJ / cm 2之间）用于退火衬底上的纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。

公开(公告)号：US10131534B2

公开(公告)日：2018-11-20

申请号：US13278080

申请日：2011-10-20

申请人： Yaoling Pan ,  Lixia Zhou

发明人： Yaoling Pan ,  Lixia Zhou

IPC分类号： G09G5/00 ,  B81B7/00 ,  B81C1/00

摘要： This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure.

公开(公告)号：US20140036340A1

公开(公告)日：2014-02-06

申请号：US13565688

申请日：2012-08-02

申请人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

发明人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

IPC分类号： G02B26/00 ,  C23C16/44

CPC分类号： G02B26/001

摘要： This disclosure provides systems, methods and apparatus for a thin film stack with surface-conditioning buffer layers. In one aspect, the thin film stack includes a plurality of thin film layers each having a thickness greater than about 10 nm and a plurality of surface-conditioning buffer layers each having a thickness between about 1 nm and about 10 nm. The surface-conditioning buffer layers are alternatingly disposed between the thin film layers. Each of the surface-conditioning buffer layers are formed with the same or substantially the same thickness and composition. In some implementations, the surface-conditioning buffer layers are formed by atomic layer deposition.

摘要翻译： 本公开提供了具有表面调节缓冲层的薄膜堆叠的系统，方法和装置。 在一个方面，薄膜堆叠包括多个厚度大于约10nm的薄膜层以及各自具有约1nm至约10nm厚度的多个表面调节缓冲层。 表面调节缓冲层交替地设置在薄膜层之间。 每个表面调节缓冲层以相同或基本上相同的厚度和组成形成。 在一些实施方案中，表面调节缓冲层通过原子层沉积形成。