公开(公告)号：US06197660B1

公开(公告)日：2001-03-06

申请号：US09301223

申请日：1999-04-29

申请人： Syun-Ming Jang ,  Ying-Ho Chen

发明人： Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： H01L2176

CPC分类号： H01L21/31111 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76229

摘要： Shallow trench isolation in which trenches having varying dimensions have been formed in a hard surface such as silicon nitride can lead to dishing inside the larger trenches. To overcome this, the trenches were first over-filled with a layer of HDPCVD oxide followed by the deposition of a relatively soft dielectric layer, using a conformal deposition method. CMP was then used to remove both the added layer and most of the original HDPCVD oxide, a small thickness of the latter being left in place. Because of the earlier influence of the added layer the resulting surface was planar and a conventional wet or dry etch could be used to remove the remaining oxide, thereby exposing the top surface and fully filling the trenches without any dishing.

摘要翻译： 浅沟槽隔离，其中具有不同尺寸的沟槽已经形成在诸如氮化硅的硬表面中，可能导致较大沟槽内的凹陷。 为了克服这一点，首先用一层HDPCVD氧化物填充沟槽，然后使用共形沉积方法沉积相对软的介电层。 然后使用CMP去除添加的层和大部分原始HDPCVD氧化物，后者的小厚度留在原位。 由于添加层的早期影响，所得表面是平面的，并且可以使用常规的湿法或干法蚀刻来除去剩余的氧化物，从而暴露顶表面并完全填充沟槽而没有任何凹陷。

公开(公告)号：US6100163A

公开(公告)日：2000-08-08

申请号：US226277

申请日：1999-01-07

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then treated the thermal silicon oxide trench liner layer by exposure to a plasma formed from a gas composition which upon plasma activation simultaneously supplies an active nitrogen containing species and an active oxygen containing species to form a plasma treated thermal silicon oxide trench liner layer. There is then formed upon the plasma treated thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material.

摘要翻译： 一种用于在硅衬底内填充沟槽的方法。 首先提供其中形成有沟槽的硅衬底。 然后将硅衬底热氧化以在沟槽内形成热氧化硅沟槽衬垫层。 然后通过暴露于由气体组合物形成的等离子体来处理热氧化硅沟槽衬里层，其在等离子体激活时同时提供含活性氮的物质和含活性氧的物质以形成等离子体处理的热氧化硅沟槽衬里层。 然后在等离子体处理的热氧化硅沟槽衬垫层上形成通过使用硅烷硅源材料的等离子体增强化学气相沉积（PECVD）方法形成的共形氧化硅中间层。 最后，通过使用臭氧氧化剂和四乙基原硅酸盐的臭氧辅助亚大气压热化学气相沉积（SACVD）方法，在保形氧化硅中间层上形成填充氧化硅沟槽填充层的间隙 （TEOS）硅源材料。

公开(公告)号：US5858588A

公开(公告)日：1999-01-12

申请号：US850133

申请日：1997-05-01

申请人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

发明人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： H01L23/544 ,  G03F9/00

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

摘要翻译： 描述了用于在集成电路晶片上恢复对准标记的掩模图案和方法，而不使用附加掩模。 掩模图案和方法提供了在平坦化的层间电介质层上形成金属层之后恢复对准标记的装置。 在用于在晶片的有源区上形成图案的掩模的端部区域中形成常规方法已经放置在单独的掩模上的图案。 为了将图案装配在掩模的端部区域中，图案被分为两部分。 当使用图案曝光一层光致抗蚀剂时，使用两个曝光步骤。

公开(公告)号：US5817567A

公开(公告)日：1998-10-06

申请号：US826710

申请日：1997-04-07

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches are then filled with a conformal layer of silicon oxide. This is followed by overcoating with a layer of a hard material such as silicon nitride or boron nitride. Next, chemical-mechanical polishing is used to remove the hard layer everywhere except where it has filled the depressions that overlie the trenches. Then, a non-selective etch is used to remove the remaining hard layer material as well as some of the silicon oxide, so that a planar surface is maintained. Finally, chemical-mechanical polishing is used a second time to remove excess silicon oxide from above the trenches' surface.

摘要翻译： 描述了一种用于在集成电路中实现浅沟槽隔离的改进方法。 该方法开始于通过图案化和蚀刻形成沟槽。 然后用保形层的氧化硅填充这些沟槽。 随后用一层硬质材料如氮化硅或氮化硼涂覆。 接下来，使用化学机械抛光来去除硬质层，除了填充了覆盖在沟槽上的凹陷之外。 然后，使用非选择性蚀刻来除去剩余的硬质层材料以​​及一些氧化硅，从而保持平坦的表面。 最后，第二次使用化学机械抛光从沟槽表面上方除去过量的氧化硅。

公开(公告)号：US5741740A

公开(公告)日：1998-04-21

申请号：US873836

申请日：1997-06-12

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/76224 ,  Y10S148/05

摘要： A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then formed upon the thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material. To provide improved properties of the gap filling silicon oxide trench fill layer the thermal silicon oxide trench liner layer may be treated with a nitrogen containing plasma prior to forming the conformal silicon oxide intermediate layer thereupon.

摘要翻译： 一种用于在硅衬底内填充沟槽的方法。 首先提供其中形成有沟槽的硅衬底。 然后将硅衬底热氧化以在沟槽内形成热氧化硅沟槽衬垫层。 然后在热氧化硅沟槽衬垫层上形成通过使用硅烷硅源材料的等离子体增强化学气相沉积（PECVD）方法形成的共形氧化硅中间层。 最后，通过使用臭氧氧化剂和四乙基原硅酸盐的臭氧辅助亚大气压热化学气相沉积（SACVD）方法，在保形氧化硅中间层上形成填充氧化硅沟槽填充层的间隙 （TEOS）硅源材料。 为了提供间隙填充氧化硅沟槽填充层的改进性能，可以在形成其之间的共形氧化硅中间层之前用含氮等离子体处理热氧化硅沟槽衬里层。

公开(公告)号：US07297632B2

公开(公告)日：2007-11-20

申请号：US11082517

申请日：2005-03-17

申请人： Chuang-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Chu-Yun Fu ,  Tung-Ching Tseng

发明人： Chuang-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Chu-Yun Fu ,  Tung-Ching Tseng

IPC分类号： H01L21/311

CPC分类号： H01L21/31053

摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.

摘要翻译： 提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。 在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件 和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

公开(公告)号：US06924238B2

公开(公告)日：2005-08-02

申请号：US10455037

申请日：2003-06-05

申请人： Tzu-Jen Chou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Shen-Nan Lee

发明人： Tzu-Jen Chou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Shen-Nan Lee

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768

CPC分类号： H01L21/31053 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/76835 ,  H01L21/7684

摘要： A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.

摘要翻译： 提供了一种用于抛光低k电介质材料层的表面的新方法和结构。 低密度和相对高孔隙率的低k电介质材料与高密度和低孔隙率的低k电介质材料组合，由此后者的高密度层在组合层的抛光之前沉积在前者的低密度层上。 组合层的抛光消除抛光的低k层电介质的剥落。 在电介质层之前，可以通过在电介质层之间形成导电互连来进一步延长该方法。

公开(公告)号：US20050090096A1

公开(公告)日：2005-04-28

申请号：US10691019

申请日：2003-10-22

申请人： Chuan-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Tung-Ching Tseng

发明人： Chuan-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Tung-Ching Tseng

IPC分类号： H01L21/00 ,  H01L21/306 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/74 ,  H01L21/762

CPC分类号： H01L21/743 ,  H01L21/76283 ,  H01L21/76286

摘要： In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation trench. Excess isolation material extends above the top surface of the intermediate structure. Part of the excess isolation material is removed until there is a predetermined thickness of isolation material remaining on the top surface of the intermediate structure. A contact opening is formed in the isolation material at the isolation trench. The contact opening extends through at least part of the intermediate structure. Contact material is deposited over the isolation material. The contact material fills the contact opening. Excess contact material, if any, that extends above the isolation material is removed. The excess isolation material is removed at least until the top surface of the intermediate structure is reached.

摘要翻译： 在本发明的方法中，提供了具有顶表面的中间结构。 形成隔离沟是中间结构。 隔离材料沉积在中间结构上。 隔离材料填充隔离沟槽。 过多的隔离材料在中间结构的顶表面上方延伸。 去除部分过量隔离材料，直到在中间结构的顶表面上剩余预定厚度的隔离材料。 在隔离沟槽处的隔离材料中形成接触开口。 接触开口延伸穿过中间结构的至少一部分。 接触材料沉积在隔离材料上。 接触材料填充接触开口。 除去在隔离材料上方延伸的过量接触材料（如果有的话）。 至少直到达到中间结构的顶表面去除多余隔离材料。

公开(公告)号：US06869858B2

公开(公告)日：2005-03-22

申请号：US10426529

申请日：2003-04-30

申请人： Syun-Ming Jang ,  Ying-Ho Chen

发明人： Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76245 ,  H01L21/31053

摘要： A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket aperture fill layer. The blanket aperture fill layer is formed employing a simultaneous deposition and sputter method. The blanket aperture fill layer fills the series of apertures to a planarizing thickness at least as high as the height of the mesas while simultaneously forming a series of protrusions of the blanket aperture fill layer corresponding with the tops of the series of mesas, where the thickness of a protrusion of the blanket aperture fill layer over a narrow mesa is less than the thickness of a protrusion of the blanket aperture fill layer over a wide mesa. The simultaneous deposition and sputter method employs a deposition rate:sputter rate ratio which provides sufficient thickness of the blanket aperture fill layer over the narrow mesa to insure coverage of the edges of the mesas. A blanket etching process is employed to remove a portion of the blanket aperture fill layer so that chemical mechanical polish (CMP) planarizing of the residual blanket aperture fill layer forms the series of patterned planarized aperture fill layers within the series of apertures.

摘要翻译： 一种用于在微电子学制造中使用的地形衬底层内的一系列孔内形成一系列图案化的平坦化孔填充层的方法。 首先提供了在微电子制造中使用的地形衬底层，其中地形衬底层包括基本上等同的高度但具有不同宽度的一系列台面，并且一系列台面由一系列孔分隔开。 然后在地形衬底层上形成橡皮布孔填充层。 使用同时沉积和溅射方法形成橡皮布孔填充层。 橡皮布孔填充层将一系列孔填充至至少与台面高度相同的平坦化厚度，同时形成与一系列台面的顶部相对应的橡皮布孔填充层的一系列突起，其中厚度 在窄的台面上的橡皮布孔填充层的突起的厚度小于宽台面上的橡皮布孔填充层的突起的厚度。 同时沉积和溅射方法采用沉积速率：溅射速率比，其提供在窄台面上的覆盖孔填充层的足够厚度，以确保台面边缘的覆盖。 采用毯式蚀刻工艺来去除橡皮布孔填充层的一部分，使得残余橡皮布孔填充层的化学机械抛光（CMP）平面化在一系列孔内形成一系列图案化的平坦化孔填充层。

公开(公告)号：US06422929B1

公开(公告)日：2002-07-23

申请号：US09541070

申请日：2000-03-31

申请人： Syun-Ming Jang ,  Ying-Ho Chen

发明人： Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： B24B2100

CPC分类号： B24B37/24 ,  B24B21/04 ,  B24B37/26 ,  B24D18/0063

摘要： A polishing pad for use in a linear polisher, and more specifically, for a linear chemical mechanical polishing apparatus that has improved polishing uniformity is described. The polishing pad is provided with a top surface for engaging a wafer surface to be polished. The top surface has a center portion and two oppositely situated edge portions. The polishing pad is further provided with a multiplicity of voids situated in the top surface of the pad body such that the top surface has a void-to-surface ratio that is greater in the two edge portions than in the center portion of the top surface. The present invention novel polishing pad provides a more uniform polishing across a wafer surface, together with an improved planarity after polishing.

摘要翻译： 描述了一种用于线性抛光机的抛光垫，更具体地说，涉及具有改善的抛光均匀性的线性化学机械抛光装置。 抛光垫设置有用于接合要抛光的晶片表面的顶表面。 顶表面具有中心部分和两个相对设置的边缘部分。 抛光垫还设置有位于衬垫主体的顶表面中的多个空隙，使得顶表面在两个边缘部分中的空隙与表面之比大于顶表面的中心部分 。 本发明的新型抛光垫在晶片表面上提供更均匀的抛光以及抛光后的改进的平面度。