公开(公告)号：US6041014A

公开(公告)日：2000-03-21

申请号：US307709

申请日：1999-05-10

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C8/00 ,  G11C8/08 ,  G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/14

摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

摘要翻译： 提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。 存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。 在擦除模式期间，向P型阱区域施加负电压，而在其它模式期间施加接地电位。

公开(公告)号：US5600592A

公开(公告)日：1997-02-04

申请号：US436563

申请日：1995-05-08

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： H01L21/8247 ,  G11C16/08 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval with such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于通过这种布置的数据擦除，数据存储和数据检索，在数据擦除期间装置加载的电压应力的水平可以是 显着减少，以允许实现设备的缩小尺寸和增强的质量。

公开(公告)号：US5392253A

公开(公告)日：1995-02-21

申请号：US918027

申请日：1992-07-24

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C8/00 ,  G11C8/08 ,  G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/14

摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.

摘要翻译： 提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。 存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。 在擦除模式期间，向P型阱区施加负电压，而在其它模式期间施加接地电位。

公开(公告)号：US5559737A

公开(公告)日：1996-09-24

申请号：US338827

申请日：1994-11-10

申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/06 ,  G11C16/28

CPC分类号： G11C7/12 ,  G11C16/28

摘要： In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.

摘要翻译： 在具有使用电平移位电路和单端读出放大器的两级读出电路的非易失性半导体存储器中，主存储单元位线电荷晶体管，主存储单元位线传输栅极晶体管， 主存储单元位线负载晶体管，虚设单元位线充电晶体管，虚设单元位线传输门晶体管和虚设单元位线负载晶体管被设置为同时满足用于对位线和虚设单元位线进行均衡的条件 以及用于均衡感测线和虚拟细胞感测线的条件。 因此，可以同时均衡位线和虚设单元位线的电位和感测线和虚设单元感测线的电位，并且可以实现高速读取操作。

公开(公告)号：US5438542A

公开(公告)日：1995-08-01

申请号：US332493

申请日：1994-10-31

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： H01L21/8247 ,  G11C16/08 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L27/02

CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

公开(公告)号：US4916665A

公开(公告)日：1990-04-10

申请号：US610704

申请日：1984-05-16

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C11/417 ,  G11C16/28

CPC分类号： G11C16/28

摘要： A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.

摘要翻译： 本发明的半导体存储器件具有多个浮动栅极存储单元。 检测器检测由解码器选择的存储在浮动栅极存储单元中的数据，并产生相应的检测信号。 负载电路放大检测信号。 放大的检测信号被提供给差分放大器。 差分放大器将放大的检测信号的电压与参考电压发生器的参考电压进行比较，并产生与浮动栅极存储器中的存储内容相对应的二进制信号。 负载电路是p沟道增强型MOS晶体管。 负载晶体管具有栅极和漏极，其连接到检​​测器和差分放大器之间的节点，并且还具有接收预定电压的源极和衬底。

公开(公告)号：US4884241A

公开(公告)日：1989-11-28

申请号：US330040

申请日：1989-03-29

申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Shinji Saito

发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Shinji Saito

IPC分类号： G11C11/41 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

CPC分类号： G11C16/28

摘要： A differential amplifier having input terminals connected to first and second nodes lying between the main nonvolatile memory cell section and the nonvolatile dummy cell circuit is used as a sense amplifier. The first and second nodes are pre-charged to a high potential level prior to the data readout operation. The memory cell section and the dummy cell circuit are set in the capacitively balanced condition, thereby making it possible to correctly read out data at a high speed.

摘要翻译： 使用具有连接到位于主非易失性存储单元部分和非易失性虚设单元电路之间的第一和第二节点的输入端的差分放大器作为读出放大器。 在数据读出操作之前，第一和第二节点被预先充电到高电位电平。 存储单元部分和虚设单元电路被设置在电容平衡状态，从而可以高速地正确地读出数据。

公开(公告)号：US4860260A

公开(公告)日：1989-08-22

申请号：US59970

申请日：1987-06-09

申请人： Shinji Saito ,  Shigeru Atsumi ,  Sumio Tanaka

发明人： Shinji Saito ,  Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC分类号： G11C29/781 ,  G11C29/24

摘要： A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.

摘要翻译： 半导体存储器件包括主存储单元阵列，冗余存储单元阵列，用于接收地址信号的接合焊盘，用于根据行地址信号选择主存储单元阵列的行的行解码器，以及交换控制器 连接以接收地址信号，其可编程为响应于特定的地址信号而禁止行解码器的选择性操作来选择冗余存储单元阵列的行。 半导体存储器件还包括用于接收测试信号的接合焊盘。 交换控制器被连接以响应于测试信号接收用于禁止行解码器的选择性操作并选择冗余存储单元阵列的行的测试信号。

公开(公告)号：US4843594A

公开(公告)日：1989-06-27

申请号：US235780

申请日：1988-08-23

申请人： Sumio Tanaka ,  Shigeru Atsumi

发明人： Sumio Tanaka ,  Shigeru Atsumi

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/22 ,  G11C16/24

CPC分类号： G11C16/24 ,  G11C16/22

摘要： A nonvolatile semiconductor memory device is disclosed comprising a bit line connected to the drain of a memory cell transistor forming a nonvolatile memory cell, a first p-channel MOS transistor, the drain and gate of the first transistor being connected to a node, and the source of the first transistor being connected to a power source potential, second and third n-channel MOS transistors connected in series between the node and a reference potential, the drain and gate of the second transistor being interconnected, and the drain and gate of the third transistor being interconnected, and a fourth n-channel MOS transistor for controlling charging of the bit line, one terminal of the drain-source path of the fourth transistor being connected to the power source potential and the other terminal being connected to the bit line, and the gate of the fourth transistor being connected to the node.

摘要翻译： 公开了一种非易失性半导体存储器件，包括连接到形成非易失性存储单元的存储单元晶体管的漏极的位线，第一p沟道MOS晶体管，第一晶体管的漏极和栅极连接到节点， 第一晶体管的源极连接到电源电位，串联连接在节点和参考电位之间的第二和第三n沟道MOS晶体管，第二晶体管的漏极和栅极互连，并且漏极和栅极 第三晶体管互连，以及第四n沟道MOS晶体管，用于控制位线的充电，第四晶体管的漏极 - 源极路径的一个端子连接到电源电位，另一个端子连接到位线 并且第四晶体管的栅极连接到节点。

公开(公告)号：US4692902A

公开(公告)日：1987-09-08

申请号：US654215

申请日：1984-09-25

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi

IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/18 ,  G11C16/06 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C7/12 ,  G11C8/18

摘要： A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.

摘要翻译： 一种半导体存储器件，其中差分放大器电路将存储信息的存储单元的位线的电位与连接有虚设单元的虚拟线的参考电位进行比较，并且检测存储在每个存储器中的信息 细胞。 半导体存储器件包括当提供芯片使能反转信号时将位线和虚拟线两者放电到低电位的电路。 因此，当提供芯片使能信号时，差分放大电路可以在位线完全充电之前检测位线电位和虚拟线电位之间的差异。 这使得可以产生芯片使能访问时间并实现更高速度的操作。