公开(公告)号：US08759899B1

公开(公告)日：2014-06-24

申请号：US13739914

申请日：2013-01-11

Applicant: Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC: H01L29/788

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

Abstract: An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

Abstract translation: 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US08759217B1

公开(公告)日：2014-06-24

申请号：US13735922

申请日：2013-01-07

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L21/00

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/32139 ,  H01L21/76838 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W−1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M−1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover Nm+1 of the landing areas and the open etch region may cover Nm of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.

Abstract translation: 一种方法形成延伸到与电介质层交错的W导电层的堆叠的导体层的层间连接。 使用一组M蚀刻掩模蚀刻堆叠以暴露W-1导电层的着陆区域。 对于从0到M-1的每个蚀刻掩模m，m，在每个修整步骤之后，存在第一蚀刻步骤，至少一个掩模修剪步骤和随后的蚀刻步骤。 蚀刻掩模可以覆盖着陆区域的Nm + 1，并且开放蚀刻区域可以覆盖着陆区域的Nm。 N等于2加上修剪步骤的数量。 可以进行修整步骤，使得增大的开口蚀刻区域覆盖附加的1 / N的着陆区域。 在去除步骤期间可以屏蔽堆叠表面的一部分以产生没有接触开口的虚拟区域。

公开(公告)号：US20130175598A1

公开(公告)日：2013-07-11

申请号：US13347331

申请日：2012-01-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/792 ,  H01L21/8239

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。

公开(公告)号：US08363476B2

公开(公告)日：2013-01-29

申请号：US13009464

申请日：2011-01-19

Applicant: Hang-Ting Lue ,  Shih-Hung Chen

Inventor： Hang-Ting Lue ,  Shih-Hung Chen

IPC: G11C16/00

CPC classification number: H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

Abstract translation: 提供了一种存储器件，其制造方法和操作方法。 存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。 堆叠结构设置在基板上。 每个堆叠结构包括串选择线，字线，接地选择线和绝缘线。 串选择线，字线和接地选择线通过绝缘线彼此分离。 通道元件设置在堆叠结构之间。 电介质元件设置在通道元件和堆叠结构之间。 源元件设置在基板的上表面和通道元件的下表面之间。 位线设置在通道元件的上表面上。

公开(公告)号：US20120276688A1

公开(公告)日：2012-11-01

申请号：US13546684

申请日：2012-07-11

Applicant: Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

Inventor： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC: H01L21/06

CPC classification number: H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

Abstract translation: 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US08243403B2

公开(公告)日：2012-08-14

申请号：US12538860

申请日：2009-08-10

Applicant: Yung-Chih Liang ,  Chih-Ting Yeh ,  Shih-Hung Chen

Inventor： Yung-Chih Liang ,  Chih-Ting Yeh ,  Shih-Hung Chen

IPC: H02H3/20 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.

Abstract translation: 提供静电放电（ESD）钳位电路。 ESD钳位电路包括第一电阻器，第二电阻器，第一晶体管，第二晶体管和第三晶体管。 ESD钳位电路的钳位装置由第三晶体管实现。 第三晶体管的寄生电容器与第二电阻器一起形成检测方案以检测ESD。 第一电阻器，第二电阻器，第一晶体管和第二晶体管形成反馈方案以控制用于放电ESD电流的第三晶体管。

公开(公告)号：US20120080657A1

公开(公告)日：2012-04-05

申请号：US13324946

申请日：2011-12-13

Applicant: Shih-Hung Chen ,  Yi-Chou Chen

Inventor： Shih-Hung Chen ,  Yi-Chou Chen

IPC: H01L47/00

CPC classification number: H01L45/122 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675 ,  Y10S977/943

Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.

Abstract translation: 与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。 结果，相对于传统的蘑菇型存储单元，每单位电流值在横向边缘内产生的热量增加。 因此，引起相变所需的电流量减少。

公开(公告)号：US08110822B2

公开(公告)日：2012-02-07

申请号：US12503624

申请日：2009-07-15

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L47/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1683

Abstract: A memory cell as described herein includes a conductive contact and a memory element comprising programmable resistance memory material overlying the conductive contact. An insulator element extends from the conductive contact into the memory element, the insulator element having proximal and distal ends and an inside surface defining an interior. The proximal end is adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end. The memory element is within the interior extending downwardly from the distal end to contact a top surface of the bottom electrode at a first contact surface. A top electrode can be separated from the distal end of the insulator element by the memory element and contact the memory element at a second contact surface having a surface area greater than that of the first contact surface.

Abstract translation: 如本文所述的存储单元包括导电接触件和包括覆盖导电接触件的可编程电阻存储器材料的存储元件。 绝缘体元件从导电触头延伸到存储元件中，绝缘元件具有近端和远端以及限定内部的内表面。 近端邻近导电接触。 底部电极接触导电接触件并且在内部从近端向上延伸。 记忆元件在内部从远端向下延伸，以在第一接触表面接触底部电极的顶表面。 顶部电极可以通过存储元件与绝缘体元件的远端分离，并且在具有大于第一接触表面的表面积的第二接触表面处接触存储元件。

公开(公告)号：US08084760B2

公开(公告)日：2011-12-27

申请号：US12426809

申请日：2009-04-20

Applicant: Hsiang-Lan Lung ,  Shih-Hung Chen ,  Stephen M. Rossnagel

Inventor： Hsiang-Lan Lung ,  Shih-Hung Chen ,  Stephen M. Rossnagel

IPC: H01L29/02

CPC classification number: H01L45/142 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: An electrode structure and a method for manufacturing an integrated circuit electrode includes forming a bottom electrode comprising a pipe-shaped member, filled with a conductive material such as n-doped silicon, and having a ring-shaped top surface. A disc-shaped insulating member is formed on the top of the pipe-shaped member by oxidizing the conductive fill. A layer of programmable resistance material, such as a phase change material, is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistance material.

Abstract translation: 电极结构和集成电路电极的制造方法包括形成包含管状部件的底部电极，该管状部件填充有诸如n掺杂硅的导电材料，并具有环形顶表面。 通过氧化导电填料，在管状构件的顶部上形成圆盘形的绝缘构件。 将一层可编程电阻材料（例如相变材料）沉积成与管状构件的顶表面接触。 与可编程电阻材料层接触的顶部电极。

公开(公告)号：US07825473B2

公开(公告)日：2010-11-02

申请号：US11186086

申请日：2005-07-21

Applicant: Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

Inventor： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract translation: 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。