公开(公告)号：US20110134705A1

公开(公告)日：2011-06-09

申请号：US12958622

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: G11C7/00

CPC classification number: G11C7/10 ,  G06F13/16 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04N21/426 ,  Y02D10/14

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 提供多路复用器以将控制信号和存储器事务多路复用到接口上，使得所述接口的多个连接由控制信号和存储器事务共享。

公开(公告)号：US20090307433A1

公开(公告)日：2009-12-10

申请号：US12284332

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08 ,  G06F12/00 ,  G06F13/24

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system memory into the cache memory. The system further comprises an event monitor for monitoring events that is connected to a path on which signals representing an event are transmitted between one or more event generating modules and a processor. In some embodiments, the event monitor initiates a pre-fetch of a portion of data in response to the event monitor detecting an event indicating the availability of the portion of data in the system memory.

Abstract translation: 公开了用于预取数据的系统和方法，其使用高速缓冲存储器来存储存储在系统存储器中的数据副本和机制，以发起从系统存储器预取数据到高速缓冲存储器中。 该系统还包括事件监视器，用于监视连接到一个路径上的事件，在该路径上，在一个或多个事件生成模块和处理器之间传送表示事件的信号。 在一些实施例中，响应于事件监视器检测指示系统存储器中的数据部分的可用性的事件，事件监视器启动对部分数据的预取。

公开(公告)号：US20090132750A1

公开(公告)日：2009-05-21

申请号：US12284336

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: The present disclosure provides systems and methods for a cache memory and a cache load circuit. The cache load circuit is capable of retrieving a portion of data from the system memory and of storing a copy of the retrieved portion of data in the cache memory. In addition, the systems and methods comprise a monitoring circuit for monitoring accesses to data in the system memory.

Abstract translation: 本公开提供了用于高速缓冲存储器和高速缓存负载电路的系统和方法。 高速缓存加载电路能够从系统存储器检索一部分数据，并将所检索的部分数据的副本存储在高速缓冲存储器中。 此外，系统和方法包括用于监视对系统存储器中的数据的访问的监视电路。

公开(公告)号：US09086870B2

公开(公告)日：2015-07-21

申请号：US13560237

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: H04L12/28 ,  G06F1/30 ,  H04W52/02

CPC classification number: G06F1/30 ,  H04W52/0277 ,  Y02D70/142 ,  Y02D70/23

Abstract: A circuit including an initiator of a transaction, an interconnect, and a controller. The controller is configured in response to a condition in a least one first part of the circuit to send a notification via the interconnect to at least one block in a second part of the circuit. The notification includes information about the condition in the first part of the circuit, the condition preventing a response to the transaction from being received by the initiator.

Abstract translation: 包括交易的发起者，互连和控制器的电路。 控制器被配置为响应于电路的至少一个第一部分中的状态，以经由互连发送通知给电路的第二部分中的至少一个块。 该通知包括关于电路的第一部分中的状况的信息，防止由发起者接收到对事务的响应的条件。

公开(公告)号：US08996815B2

公开(公告)日：2015-03-31

申请号：US13560491

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: An integrated circuit (IC) may include a cache memory, and a cache memory controller coupled to the cache memory. The cache memory controller may be configured to receive a cache miss associated with a memory location, issue pre-fetch requests, each pre-fetch request having a quality of service (QoS), and determine if a pre-fetch request has issued for the memory location associated with the cache miss.

Abstract translation: 集成电路（IC）可以包括高速缓冲存储器和耦合到高速缓冲存储器的高速缓冲存储器控制器。 缓存存储器控制器可以被配置为接收与存储器位置相关联的高速缓存未命中，发出预取请求，每个预取请求具有服务质量（QoS），并且确定是否为 与高速缓存未命中关联的存储器位置。

公开(公告)号：US08725987B2

公开(公告)日：2014-05-13

申请号：US12284329

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed for pre-fetching data into a cache memory system. These systems and methods comprise retrieving a portion of data from a system memory and storing a copy of the retrieved portion of data in a cache memory. These systems and methods further comprise monitoring data that has been placed into pre-fetch memory.

Abstract translation: 公开了用于将数据预取入高速缓冲存储器系统的系统和方法。 这些系统和方法包括从系统存储器检索数据的一部分并且将检索到的数据部分的副本存储在高速缓冲存储器中。 这些系统和方法还包括监视已经被放置到预取存储器中的数据。

公开(公告)号：US08653638B2

公开(公告)日：2014-02-18

申请号：US12958646

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: H01L23/02 ,  H01L29/40 ,  H01L21/00

CPC classification number: G06F13/4265 ,  G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311 ,  Y02D10/14 ,  Y02D10/151

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater than a width of the interface. At least one of the first and second dies performs a configurable grouping so as to provide a plurality of groups of control signals. The signals within a group are transmitted across the interface together.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口被配置为传送多个控制信号。 控制信号的数量大于接口的宽度。 第一和第二模具中的至少一个模具执行可配置分组，以便提供多组控制信号。 组内的信号一起通过接口传输。

公开(公告)号：US08610258B2

公开(公告)日：2013-12-17

申请号：US12958639

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: H01L23/22 ,  H01L29/40

CPC classification number: G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 采样电路在接口传输之前对控制信号进行采样。 取决于与相应控制信号相关联的至少一个服务质量参数来控制采样电路。

公开(公告)号：US08521937B2

公开(公告)日：2013-08-27

申请号：US13028383

申请日：2011-02-16

Applicant: Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

Inventor： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

IPC: G06F13/14 ,  G06F13/38

CPC classification number: G06F13/385 ,  A01C7/04 ,  A01C7/20 ,  G06F15/173 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.

Abstract translation: 包装包括模具和至少一个另外的模具。 管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。 芯片还具有映射电路，其被配置为接收包括至少第一源标识信息的事务请求，其中第一源标识信息与另外裸片上的事务请求的源相关联。 映射电路被配置为修改事务请求以用本地源标识信息替换第一源标识信息，其中本地源标识信息与映射电路相关联。 映射电路被配置为修改所接收的事务请求以在另外的字段中提供所述第一源标识信息。

公开(公告)号：US20130103912A1

公开(公告)日：2013-04-25

申请号：US13489920

申请日：2012-06-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0815 ,  G06F12/0817 ,  G06F13/1663

Abstract: An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part includes at least one second cache memory configured to request access to said memory. The first directory is configured to use a first coherency protocol for the at least one first cache memory and a second different coherency protocol for the at least one second memory.

Abstract translation: 一种装置包括第一部分和第二部分。 第一部分包括用于访问存储器，至少一个第一高速缓冲存储器和第一目录的存储器控​​制器。 第二部分包括被配置为请求访问所述存储器的至少一个第二高速缓存存储器。 第一目录被配置为对于至少一个第一高速缓存存储器使用第一一致性协议，以及对于至少一个第二存储器使用第二不同一致性协议。