公开(公告)号：US07279392B2

公开(公告)日：2007-10-09

申请号：US11046876

申请日：2005-02-01

Applicant: Seung-Hwan Lee ,  Kyoung-Ryul Yoon ,  Han-Mei Choi ,  Dae-Sik Choi ,  Ki-Yeon Park ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo

Inventor： Seung-Hwan Lee ,  Kyoung-Ryul Yoon ,  Han-Mei Choi ,  Dae-Sik Choi ,  Ki-Yeon Park ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo

IPC: H01L21/20 ,  H01L29/00

CPC classification number: C23C16/45529 ,  C23C16/308 ,  C23C16/405 ,  H01L27/11502 ,  H01L27/11507

Abstract: A thin film structure and a capacitor using the film structure and methods for forming the same. The thin film structure may include a first film formed on a substrate using a first reactant and an oxidant for oxidizing the first reactant. A second film may be formed on the first film to suppress crystallization of the first film. A capacitor may include a dielectric layer, which may further include the first thin film and the second thin film.

Abstract translation: 薄膜结构和使用该薄膜结构的电容器及其形成方法。 薄膜结构可以包括使用第一反应物和用于氧化第一反应物的氧化剂在基底上形成的第一膜。 可以在第一膜上形成第二膜以抑制第一膜的结晶。 电容器可以包括电介质层，其可以进一步包括第一薄膜和第二薄膜。

公开(公告)号：US20060204681A1

公开(公告)日：2006-09-14

申请号：US11369791

申请日：2006-03-07

Applicant: Keon-Il Kim ,  Sung-Tae Kim ,  Ki-Cheol Yoon ,  Nam Ki ,  Hunkyun Pak ,  Jae-Chul Jung

Inventor： Keon-Il Kim ,  Sung-Tae Kim ,  Ki-Cheol Yoon ,  Nam Ki ,  Hunkyun Pak ,  Jae-Chul Jung

IPC: G02F1/1335 ,  C09K19/36

CPC classification number: C09K19/2007 ,  C09K19/588 ,  C09K2019/0448 ,  C09K2219/03 ,  G02B5/3016 ,  Y10T428/10 ,  Y10T428/1005 ,  Y10T428/1036 ,  Y10T428/1041

Abstract: Disclosed is a broadband reflection type brightness enhancement polarizer, which includes a cholesteric liquid crystal film laminate having a broadband selective reflecting wavelength range in which a plurality of cholesteric liquid crystal films having selective reflecting wavelength ranges different from each other by having different mixture ratios of a curable nematic liquid crystal compound expressed by the chemical formula 1 and a curable chiral compound expressed by the chemical formula 2 are laminated; and a film having ¼λ phase difference laminated on one surface of the cholesteric liquid crystal film laminate. This polarizer has wide selective reflecting wavelength ranges of the cholesteric liquid crystal films composing the polarizer, so the entire visible ray range can be covered just by laminating several cholesteric liquid crystal films. Accordingly, the polarizer may be manufactured relatively thinner, so the brightness can be greatly improved when the polarizer is applied to a liquid crystal display.

公开(公告)号：US07094712B2

公开(公告)日：2006-08-22

申请号：US10793818

申请日：2004-03-08

Applicant: Ki-Vin Im ,  Ki-Yeon Park ,  Jae-Hyun Yeo ,  In-Sung Park ,  Seung-Hwan Lee ,  Young-Sun Kim ,  Sung-Tae Kim

Inventor： Ki-Vin Im ,  Ki-Yeon Park ,  Jae-Hyun Yeo ,  In-Sung Park ,  Seung-Hwan Lee ,  Young-Sun Kim ,  Sung-Tae Kim

IPC: H01L21/31

CPC classification number: H01L21/0228 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Disclosed is a method for forming metal oxide dielectric layers, more particularly HfO2 dielectric layers, using an atomic layer deposition (ALD) method in which a series of thin intermediate layers are formed and treated with one or more oxidizers and nitrogents before the next intermediate layer is formed on the substrate. The intermediate oxidation treatments reduce the number of organic contaminants incorporated into the metal oxide layer from the organometallic precursors to produce a dielectric layer having improved current leakage characteristics. The dielectric layers formed in this manner remain susceptible to crystallization if exposed to temperatures much above 550° C., so subsequent semiconductor manufacturing processes should be modified or eliminated to avoid such temperatures or limit the duration at such temperatures to maintain the performance of the dielectric materials.

Abstract translation: 公开了一种使用原子层沉积（ALD）方法形成金属氧化物电介质层，更具体地是HfO 2 电介质层的方法，其中形成一系列薄的中间层并用一个或多个 在下一个中间层之前形成氧化剂和氮。 中间氧化处理减少了从有机金属前体引入到金属氧化物层中的有机污染物的数量，以产生具有改善的电流泄漏特性的电介质层。 如果暴露在高于550℃的温度下，以这种方式形成的电介质层仍然易于结晶，因此随后的半导体制造工艺应当被修改或消除以避免这种温度或限制在这样的温度下的持续时间以保持电介质的性能 材料

公开(公告)号：US06992346B2

公开(公告)日：2006-01-31

申请号：US10807000

申请日：2004-03-23

Applicant: Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Jongwan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

Inventor： Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Jongwan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

IPC: H01L29/096

CPC classification number: H01L21/32051 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

Abstract: A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

Abstract translation: 导电接触插塞延伸穿过电介质层中的开口以接触衬底并且包括延伸到邻近开口的电介质层上的加宽焊盘部分。 欧姆图案设置在插头的焊盘部分上，并且阻挡图案设置在欧姆图案上。 凹陷的第一电容器电极设置在阻挡图案上并且限定了远离基板的空腔。 电容器电介质层符合第一电容器电极的表面，并且第二电容器电极设置在与第一电容器电极相对的电容器电介质层上。 欧姆图案的侧壁，接触塞的阻挡图案和焊盘部分可以是基本上共面的，并且该器件还可以包括符合至少欧姆图案的侧壁，阻挡图案和焊盘部分的蚀刻停止层 接触插头。 描述相关的制造方法。

公开(公告)号：US06897106B2

公开(公告)日：2005-05-24

申请号：US10713577

申请日：2003-11-12

Applicant: Ki-Yeon Park ,  Sung-Tae Kim ,  Young-Sun Kim ,  In-Sung Park ,  Jae-Hyun Yeo ,  Ki-Vin Im

Inventor： Ki-Yeon Park ,  Sung-Tae Kim ,  Young-Sun Kim ,  In-Sung Park ,  Jae-Hyun Yeo ,  Ki-Vin Im

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A semiconductor memory device that includes a composite Al2O3/HfO2 dielectric layer with a layer thickness ratio greater than or equal to 1, and a method of manufacturing the capacitor are provided. The capacitor includes a lower electrode, a composite dielectric layer including an Al2O3 dielectric layer and an HfO2 dielectric layer sequentially formed on the lower electrode, the Al2O3 dielectric layer having a thickness greater than or equal to the HfO2 dielectric layer, and an upper electrode formed on the composite dielectric layer. The Al2O3 dielectric layer has a thickness of 30-60 Å. The HfO2 dielectric layer has a thickness of 40 Å or less.

Abstract translation: 一种半导体存储器件，其包括层厚度比大于或等于1的复合Al 2 O 3 / HfO 2 电介质层， 并提供一种制造该电容器的方法。 电容器包括下电极，复合电介质层，其包括依次形成在其上的Al 2 O 3 3电介质层和HfO 2 N 2介电层 下电极，具有大于或等于HfO 2 2电介质层的厚度的Al 2 O 3 3 电介质层，以及形成的上电极 在复合介电层上。 Al 2 O 3介电层具有30-60埃的厚度。 HfO 2 2介电层的厚度为40以下。

公开(公告)号：US06186779B1

公开(公告)日：2001-02-13

申请号：US09334133

申请日：1999-06-15

Applicant: Hae-Moon Choi ,  Sung-Tae Kim ,  Hyun-Kuk Ko ,  Dae-Moon Kim

Inventor： Hae-Moon Choi ,  Sung-Tae Kim ,  Hyun-Kuk Ko ,  Dae-Moon Kim

IPC: F27D500

CPC classification number: H01L21/68721 ,  C30B25/12 ,  C30B31/14 ,  H01L21/68785

Abstract: A clamp holds a semiconductor wafer during an Al reflow process. The clamp is made of a ceramic material, and thereby clamp surface roughening which damages semiconductor wafers and other damaging of the wafer caused by the deformation of the clamp are avoided. A sloped surface of the clamp pad can also reduce the damage on the wafer by reducing the contact area between the clamp pad and the wafer. In addition, the clamp has several features that can reduce heat dissipation from the wafer to outside during the Al reflow. Slots formed on the pad reduce the amount of heat conduction through the clamp, and the polished inner surface of the clamp cap reflects the heat radiated from the wafer back to the wafer.

Abstract translation: 夹具在Al回流焊过程中保持半导体晶片。 夹具由陶瓷材料制成，从而避免了由于夹具的变形而损坏半导体晶片和损坏晶片的表面粗糙化。 夹持垫的倾斜表面还可以通过减小夹紧垫和晶片之间的接触面积来减小晶片上的损坏。 此外，夹具具有几个特征，可以在铝回流期间减少晶片向外部的散热。 形成在垫上的槽减少了通过夹具的热传导量，并且夹持盖的抛光内表面将从晶片辐射的热量反射回晶片。

公开(公告)号：US6077772A

公开(公告)日：2000-06-20

申请号：US270174

申请日：1999-03-16

Applicant: In-Seon Park ,  Sung-Tae Kim ,  Du-Hwan Lee ,  Won-Goo Hur

Inventor： In-Seon Park ,  Sung-Tae Kim ,  Du-Hwan Lee ,  Won-Goo Hur

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76856 ,  H01L21/76843 ,  H01L21/76882

Abstract: A method of forming a metal interconnection includes the steps of forming a first conductive layer on a substrate, and forming an insulating layer on the first conductive layer and on the substrate. A contact hole is formed in the insulating layer thereby exposing a portion of the first conductive layer, a barrier layer is formed on the exposed portion of the first conductive layer in the contact hole, and a thermal treatment is performed on the barrier layer. After the step of performing the thermal treatment, a wetting layer is formed on a sidewall of the contact hole, and a second conductive layer is formed on the barrier layer and on the wetting layer in the contact hole.

Abstract translation: 形成金属互连的方法包括以下步骤：在衬底上形成第一导电层，并在第一导电层和衬底上形成绝缘层。 在绝缘层中形成接触孔，从而露出第一导电层的一部分，在接触孔中的第一导电层的暴露部分上形成阻挡层，并对阻挡层进行热处理。 在进行热处理的步骤之后，在接触孔的侧壁上形成润湿层，并且在阻挡层和接触孔中的润湿层上形成第二导电层。

公开(公告)号：US5657802A

公开(公告)日：1997-08-19

申请号：US565853

申请日：1995-12-01

Applicant: Sung-Tae Kim

Inventor： Sung-Tae Kim

IPC: B65D47/08 ,  B65D77/24 ,  G01F19/00 ,  B65B1/04

CPC classification number: B65D77/245 ,  B65D47/0866 ,  G01F19/002 ,  B65D2251/1075

Abstract: An improved plug structure for aquarium fish food containers is disclosed. The plug of this invention has two depressions for receiving a detachable tap and a detachable spoon respectively. The tap is pivoted to the spoon and easily opened by a one touch motion. Both the spoon and the tap can be easily separated from the plug body at the same time. The above plug thus allows the fixed amount of food to be taken out of the food container thereby saving food. The plug also prevents food from dropping when measuring the fixed amount of food using the spoon.

Abstract translation: 公开了一种用于水族箱鱼食品容器的改进的塞子结构。 本发明的插头具有两个凹部，用于分别接收可拆卸的水龙头和可拆卸的勺子。 水龙头被枢转到勺子，并且通过一触式动作容易地打开。 勺子和水龙头可以同时容易地从插头体分离。 因此，上述插头允许将固定数量的食物从食物容器中取出，从而节省食物。 当使用勺子测量固定量的食物时，塞子还防止食物掉落。

公开(公告)号：US20110260714A1

公开(公告)日：2011-10-27

申请号：US12866447

申请日：2009-08-28

Applicant: Gi-Yeop Kim ,  Kyo-Won Jung ,  Cho-Soo Lee ,  Sung-Tae Kim ,  Yong-Jin Kang

Inventor： Gi-Yeop Kim ,  Kyo-Won Jung ,  Cho-Soo Lee ,  Sung-Tae Kim ,  Yong-Jin Kang

IPC: G01B7/30

CPC classification number: G01B7/30 ,  G01D5/2291

Abstract: The present invention provides an inductive angle sensor with improved common mode noise rejection and a signal processing method of the same, which can improve electromagnetic compatibility (EMC) characteristics and obtain an accurate output value by eliminating common mode noise. The signal processing method includes adding signals obtained from a pair of receiver coils by an adder, subtracting the signal obtained from one of the pair of receiver coils from the signal obtained from the other receiver coil by a subtracter, multiplying the value obtained from the adder by the value obtained from the subtracter by a first multiplier, multiplying the value obtained from the subtracter by itself by a second multiplier, and dividing the value obtained from the first multiplier by the value obtained from the second multiplier by a divider.

Abstract translation: 本发明提供一种具有改进的共模噪声抑制的电感角度传感器及其信号处理方法，其可以通过消除共模噪声来改善电磁兼容性（EMC）特性并获得准确的输出值。 信号处理方法包括通过加法器将从一对接收器线圈获得的信号相加，通过减法器从从另一个接收器线圈获得的信号中减去从该对接收器线圈中的一个获得的信号，将从加法器获得的值相乘 通过第一乘法器从减法器获得的值，将从减法器获得的值乘以第二乘法器，并将从第一乘法器获得的值除以由第二乘法器获得的值除以分频器。

公开(公告)号：US07842569B2

公开(公告)日：2010-11-30

申请号：US11618155

申请日：2006-12-29

Applicant: Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

Inventor： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

IPC: H01L21/00

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract translation: 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。