公开(公告)号：US12176346B2

公开(公告)日：2024-12-24

申请号：US17804565

申请日：2022-05-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Szu-Lin Liu ,  Jaw-Juinn Horng ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Ya Yun Liu

IPC: H01L27/082 ,  G01K7/01 ,  H01L21/8228 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

公开(公告)号：US12176338B2

公开(公告)日：2024-12-24

申请号：US18519486

申请日：2023-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Hsin Tsai ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092

Abstract: A semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The drain/source contact extends in the second direction and is connected to the second conductor. The at least one conductive via connects the first conductor and the second conductor through the third conductor.

公开(公告)号：US12153868B2

公开(公告)日：2024-11-26

申请号：US18064027

申请日：2022-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shang-Chih Hsieh ,  Chun-Fu Chen ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Hsiang-Jen Tseng

IPC: G06F30/392 ,  H01L21/768 ,  H01L27/02 ,  H01L27/118

Abstract: An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.

公开(公告)号：US12142637B2

公开(公告)日：2024-11-12

申请号：US17575590

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Yi-Lin Fan ,  Hui-Zhong Zhuang ,  Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/522 ,  H01L29/40 ,  H01L29/423

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

公开(公告)号：US12073163B2

公开(公告)日：2024-08-27

申请号：US17405626

申请日：2021-08-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Hong Gao ,  Hui-Zhong Zhuang

IPC: G06F30/30 ,  G06F30/392 ,  H01L21/04 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L21/041 ,  H01L27/0207

Abstract: An integrated circuit (IC) includes a first, second and third semiconductor cell regions. The first cell region includes a first active region having a first dopant type. The second semiconductor cell region abuts the first cell region in a second direction, and includes second and third active regions having correspondingly a second dopant type and the first dopant type. The second active region is between the first and third active regions. The third cell region abuts the second cell region in the second direction, and includes a fourth active region having the second dopant type. The third active region is between the fourth active region and the second active region. The second semiconductor cell region has a height 2H, and the first, second and third semiconductor cell regions collectively have a height 3H.

公开(公告)号：US12019969B2

公开(公告)日：2024-06-25

申请号：US17383153

申请日：2021-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chi-Yu Lu

IPC: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3953 ,  G06F119/18

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3953 ,  G06F2119/18

Abstract: An integrated circuit includes at least one source/drain (S/D) line extending in second direction in a cell of the integrated circuit. The integrated circuit further includes a conductive element extending in a first direction in the cell of the integrated circuit, the first direction being perpendicular to the second direction. The integrated circuit further includes a power rail extending over the conductive element, wherein the power rail includes a first power rail portion and a second power rail portion, and an inner edge of the first power rail portion is offset from an inner edge of the second power rail portion, wherein the first power rail portion has a first edge and the second power rail portion has a second edge on the same side as the first edge of the first power rail portion, and the first edge and the second edge are laterally separated.

公开(公告)号：US12009362B2

公开(公告)日：2024-06-11

申请号：US18360539

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L27/06 ,  G06F30/392 ,  G06F30/394 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0694 ,  G06F30/392 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

公开(公告)号：US11790151B2

公开(公告)日：2023-10-17

申请号：US17885106

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Hui-Zhong Zhuang ,  Meng-Kai Hsu ,  Pin-Dai Sue ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu ,  Jung-Chou Tsai

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F119/18

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

公开(公告)号：US11790148B2

公开(公告)日：2023-10-17

申请号：US17117986

申请日：2020-12-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Zhong Zhuang ,  Ting-Wei Chang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Shun Li Chen

IPC: G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

公开(公告)号：US11694013B2

公开(公告)日：2023-07-04

申请号：US17860985

申请日：2022-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: G06F30/392 ,  H01L27/02 ,  H01L27/092

CPC classification number: G06F30/392 ,  H01L27/0207 ,  H01L27/092

Abstract: An integrated circuit includes a first and a set of conductive traces, and a first conductive feature. The second set of conductive traces includes a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor, and a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a first n-type transistor. The first conductive feature corresponds to at least a first contact of a first dummy transistor. The first conductive trace of the second set of conductive traces is electrically coupled to the second conductive trace of the second set of conductive traces by at least the first conductive feature. The first n-type transistor being part of a first transmission gate. The first p-type transistor being part of a second transmission gate.