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    High linearity phase interpolator
    31.
    发明授权
    High linearity phase interpolator 有权

    公开(公告)号：US10855294B2

    公开(公告)日：2020-12-01

    申请号：US15346524

    申请日：2016-11-08

    Applicant: Texas Instruments Incorporated

    Inventor： Baher Haroun ,  Wenting Zhou ,  Kai Yiu Tam ,  Reza Hoshyar ,  Ali Kiaei

    IPC: H03L7/16 ,  H03K23/00

    Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

    Low-power low-phase-noise oscillator
    32.
    发明授权
    Low-power low-phase-noise oscillator 有权

    公开(公告)号：US10804848B2

    公开(公告)日：2020-10-13

    申请号：US15366149

    申请日：2016-12-01

    Applicant: Texas Instruments Incorporated

    Inventor： Seong-Ryong Ryu ,  Ali Kiaei

    IPC: H03B5/32 ,  H03B5/12 ,  H03B5/30 ,  H03B5/36

    Abstract: The present disclosure describes a low-power, low-phase-noise (LPLPN) oscillator. The LPLPN oscillator includes a resonator load, an amplifier stage, and a loop gain control circuit. The resonator load is structured to resonate at a primary resonant frequency. The amplifier stage is coupled with the resonator load to develop a loop gain that peaks at the primary resonant frequency. The loop gain control circuit is coupled with the amplifier stage, and it is structured to regulate the loop gain for facilitating the amplifier stage to generate an oscillation signal at the primary resonant frequency and suppress a noise signal at a parasitic parallel resonant frequency (PPRF).

    PULLABLE CLOCK OSCILLATOR
    33.
    发明申请
    PULLABLE CLOCK OSCILLATOR 审中-公开

    公开(公告)号：US20200274485A1

    公开(公告)日：2020-08-27

    申请号：US16870582

    申请日：2020-05-08

    Applicant: Texas Instruments Incorporated

    Inventor： Ben-yong Zhang ,  Seong-Ryong Ryu ,  Ali Kiaei ,  Ting-Ta Yen ,  Kai Yiu Tam

    IPC: H03B1/04 ,  H03B5/32 ,  H03B1/02 ,  H03L7/099 ,  H03B5/36

    Abstract: A clock oscillator includes with a pullable BAW oscillator to generate an output signal with a target frequency. The BAW oscillator is based on a BAW resonator and voltage-controlled variable load capacitance, responsive to a capacitance control signal to provide a selectable load capacitance. An oscillator driver (such as a differential negative gm transconductance amplifier), is coupled to the BAW oscillator to provide an oscillation drive signal. The BAW oscillator is responsive to the oscillation drive signal to generate the output signal with a frequency based on the selectable load capacitance. The oscillator driver can include a bandpass filter network with a resonance frequency substantially at the target frequency.

    FRACTIONAL FREQUENCY CLOCK DIVIDER WITH DIRECT DIVISION
    35.
    发明申请
    FRACTIONAL FREQUENCY CLOCK DIVIDER WITH DIRECT DIVISION 审中-公开

    公开(公告)号：US20180097523A1

    公开(公告)日：2018-04-05

    申请号：US15281617

    申请日：2016-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Reza Hoshyar ,  Wenting Zhou ,  Ali Kiaei ,  Baher Haroun ,  Ahmad Bahai

    IPC: H03L7/197

    CPC classification number: H03L7/1976 ,  H03L7/16 ,  H03L7/18 ,  H03L7/1806 ,  H03L7/197

    Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

    Method and circuitry for CMOS transconductor linearization
    36.
    发明授权
    Method and circuitry for CMOS transconductor linearization 有权
    CMOS跨导线性化的方法和电路

    公开(公告)号：US09531335B2

    公开(公告)日：2016-12-27

    申请号：US14818882

    申请日：2015-08-05

    Applicant: Texas Instruments Incorporated

    Inventor： Harish Kundur Subramaniyan ,  Eric Klumperink ,  Venkatesh Srinivasan ,  Ali Kiaei ,  Bram Nauta

    IPC: G06G7/12 ,  H03F3/193 ,  H03F1/30 ,  H03F1/32 ,  H03F1/02 ,  H03F3/30

    CPC classification number: H03F3/193 ,  H03F1/0261 ,  H03F1/301 ,  H03F1/308 ,  H03F1/3205 ,  H03F1/3217 ,  H03F3/3022 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/30078 ,  H03F2203/30111

    Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor. A low impedance bypass circuit re-circulates second order distortion current that is induced by second-order distortion in drain currents of the first P-channel transistor and the first N-channel transistor, through the first N-channel transistor and first P-channel transistor.

    Abstract translation: 在包括第一N沟道晶体管和第一P沟道晶体管的CMOS跨导电路中，三阶失真减小，第一N沟道晶体管和第一P沟道晶体管的栅极被耦合以接收输入信号。 第一N沟道晶体管和第一P沟道晶体管的漏极耦合到输出导体。 第一退化电阻器耦合在第一P沟道晶体管的源极和第一电源电压之间，而第二退化电阻耦合在第一N沟道晶体管的源极和第二电源电压之间。 第一低阻抗旁路电路耦合在第一P沟道晶体管和第一N沟道晶体管的源极之间。 低阻抗旁路电路通过第一N沟道晶体管和第一P沟道重新循环由第二P沟道晶体管和第一N沟道晶体管的漏极电流引起的二阶失真引起的二阶失真电流 晶体管。

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