公开(公告)号：US20140252485A1

公开(公告)日：2014-09-11

申请号：US13789477

申请日：2013-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Abstract translation: 第一类型的杂质原子通过栅极和薄栅极电介质注入到在沟道区的中间点处基本上仅具有第一类型的杂质原子的沟道区，以增加第一类杂质的平均掺杂浓度 通道区域中的原子来调节晶体管的阈值电压。

公开(公告)号：US08753944B2

公开(公告)日：2014-06-17

申请号：US13766847

申请日：2013-02-14

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Hornung ,  Terry James Bordelon, Jr. ,  Amitava Chatterjee

IPC: H01L21/336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Abstract translation: 制造金属氧化物半导体（MOS）晶体管的方法包括提供具有掺杂有第二掺杂剂类型的衬底表面的衬底和在衬底表面上的栅极堆叠，以及在衬底表面上的掩模图案，其暴露部分 用于离子注入的衬底表面。 第一种口袋植入使用具有衬底表面上的掩模图案的第二掺杂剂类型。 至少一个逆向栅极边缘二极管漏极（GDL）还原袋注入在衬底表面上使用具有掩模图案的第一掺杂剂类型。 第一口袋植入物和逆行GDL还原袋植入物进行退火。 在退火之后，第一口袋植入件提供第一袋区域，并且逆行GDL减少袋植入物提供与第一袋区域的重叠，以在第一袋区域内形成第一反向袋部分。

公开(公告)号：US10608110B2

公开(公告)日：2020-03-31

申请号：US15679908

申请日：2017-08-17

Applicant: Texas Instruments Incorporated

Inventor： Amitava Chatterjee

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.

公开(公告)号：US09865507B2

公开(公告)日：2018-01-09

申请号：US15204428

申请日：2016-07-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/423 ,  H01L27/092 ,  H01L27/10 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US09583596B2

公开(公告)日：2017-02-28

申请号：US14949241

申请日：2015-11-23

Applicant: Texas Instruments Incorporated

Inventor： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L29/861 ,  H01L29/08 ,  G06F17/50 ,  H01L29/10

CPC classification number: H01L29/66681 ,  G06F17/5081 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/861

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract translation: 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

公开(公告)号：US09577094B2

公开(公告)日：2017-02-21

申请号：US14885637

申请日：2015-10-16

Applicant: Texas Instruments Incorporated

Inventor： Shaoping Tang ,  Amitava Chatterjee ,  Imran Mahmood Khan ,  Kaiping Liu

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/06 ,  H01L21/28 ,  H01L29/49 ,  H01L29/10

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract translation: 集成电路和方法包括具有改进的CHC可靠性的DEMOS晶体管，其在DEMOS栅极下具有较低电阻表面沟道，其转变到DEMOS晶体管栅极的漏极边缘下方的较低电阻的地下通道。

公开(公告)号：US20150380551A1

公开(公告)日：2015-12-31

申请号：US14846398

申请日：2015-09-04

Applicant: Texas Instruments Incorporated

Inventor： Amitava Chatterjee

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/3105 ,  H01L29/49 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7833 ,  H01L21/28123 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/823828 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66568

Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.

Abstract translation: 具有降低的亚阈值导通的金属氧化物半导体（MOS）晶体管及其制造方法。 在这些晶体管中制造晶体管栅极结构，其形状和尺寸与从隔离电介质结构和晶体管有源区之间的界面重叠到有源区上。 因此，在隔离到有源接口处不能获得最小通道长度导通，而是沿着该界面的通道长度基本上延长，从而减少断态传导。

公开(公告)号：US09202912B2

公开(公告)日：2015-12-01

申请号：US14576693

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Shaoping Tang ,  Amitava Chatterjee ,  Imran Mahmood Khan ,  Kaiping Liu

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract translation: 集成电路和方法包括具有改进的CHC可靠性的DEMOS晶体管，其具有在DEMOS栅极下方的较低电阻表面沟道，其转变到DEMOS晶体管栅极的漏极边缘下方的较低电阻的地下通道。

公开(公告)号：US20140183630A1

公开(公告)日：2014-07-03

申请号：US14142006

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Amitava Chatterjee ,  Imran Khan

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823456

Abstract: An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.

Abstract translation: 可以通过将MOS晶体管和DEMOS晶体管的源/漏区相同的导电类型的掺杂剂通过MOS晶体管的栅极并通过栅极形成包含具有相同极性的MOS晶体管和DEMOS晶体管的集成电路 的DEMOS晶体管。 注入的掺杂剂从DEMOS晶体管栅极的漏极侧边缘封闭。 注入的掺杂剂在DEMOS晶体管栅极的DEMOS晶体管的扩展漏极的漂移区域内形成漏极增强区域。

公开(公告)号：US20140061785A1

公开(公告)日：2014-03-06

申请号：US14073530

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

IPC: H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66681 ,  G06F17/5081 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/861

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract translation: 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。