公开(公告)号：US11734382B2

公开(公告)日：2023-08-22

申请号：US17331215

申请日：2021-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Sai Ram Prakash Jayanthi

IPC: G06F17/14 ,  G06F7/76 ,  G06F13/28

CPC classification number: G06F17/142 ,  G06F7/768 ,  G06F13/287

Abstract: A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

公开(公告)号：US11714603B2

公开(公告)日：2023-08-01

申请号：US17156731

申请日：2021-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

IPC: G06F7/24 ,  G06F5/06

CPC classification number: G06F7/24 ,  G06F5/065 ,  G06F2207/228

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

公开(公告)号：US20220206133A1

公开(公告)日：2022-06-30

申请号：US17138549

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Karthik Subburaj ,  Sreekiran Samala ,  Indu Prathapan

IPC: G01S13/34 ,  G01S7/03 ,  G01S7/35 ,  H03C3/09 ,  H03L7/087 ,  H03L7/099

Abstract: In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.

公开(公告)号：US20200379649A1

公开(公告)日：2020-12-03

申请号：US16995542

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Puneet Sabbarwal ,  Indu Prathapan

IPC: G06F3/06 ,  G06F30/30

Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.

公开(公告)号：US20200210287A1

公开(公告)日：2020-07-02

申请号：US16790444

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US10599514B2

公开(公告)日：2020-03-24

申请号：US15844259

申请日：2017-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abishek Ganapati Karkisaval

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US20190331765A1

公开(公告)日：2019-10-31

申请号：US16442152

申请日：2019-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Rao ,  Karthik Ramasubramanian ,  Indu Prathapan ,  Raghu Ganesan ,  Pankaj Gupta

IPC: G01S7/02 ,  G01S13/58 ,  G01S7/35 ,  G01S13/42 ,  G01S13/34 ,  H04B15/02 ,  H04L27/10

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

公开(公告)号：US20180227157A1

公开(公告)日：2018-08-09

申请号：US15942614

申请日：2018-04-02

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

IPC: H04L27/26

CPC classification number: H04L27/2624

Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

公开(公告)号：US20160127161A1

公开(公告)日：2016-05-05

申请号：US14528660

申请日：2014-10-30

Applicant: Texas Instruments Incorporated

Inventor： Sriram Murali ,  Indu Prathapan ,  Pankaj Gupta ,  Zahir Ibrahim Parkar ,  Sundarrajan Rangachari

IPC: H04L27/156 ,  H04L27/38 ,  H04L27/34 ,  H04L27/14

CPC classification number: H04L27/1566 ,  H04L27/3455 ,  H04W52/0229 ,  Y02D70/00

Abstract: A weather band receiver, which may be part of an FM receiver, is disclosed. FSK-encoded data units in an alert packet transmission are detected using a quadrature matched filter circuit. At least one FSK-encoded data unit is captured from the alert packet transmission. Soft quantized bits are extracted from the FSK-encoded data units. The soft quantized bits are saved to memory and used to recover an alert message. Soft quantized bits from two or more FSK-encoded data units may be combined before recovering the alert message.

Abstract translation: 公开了可以是FM接收机的一部分的气象带接收机。 使用正交匹配滤波器电路检测警报分组传输中的FSK编码数据单元。 从警报包传输中捕获至少一个FSK编码的数据单元。 从FSK编码数据单元提取软量化比特。 软量化位保存到存储器中，用于恢复警报消息。 可以在恢复警报消息之前组合来自两个或更多个FSK编码数据单元的软量化比特。