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    Memory pipeline control in a hierarchical memory system
    32.
    发明授权
    Memory pipeline control in a hierarchical memory system 有权

    公开(公告)号：US11580024B2

    公开(公告)日：2023-02-14

    申请号：US17492776

    申请日：2021-10-04

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    Nested loop control
    33.
    发明授权
    Nested loop control 有权

    公开(公告)号：US11442709B2

    公开(公告)日：2022-09-13

    申请号：US16983429

    申请日：2020-08-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

    IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

    Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
    39.
    发明申请
    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING 审中-公开

    公开(公告)号：US20200371888A1

    公开(公告)日：2020-11-26

    申请号：US16988500

    申请日：2020-08-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

    IPC: G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/36 ,  G06F11/07

    Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

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