公开(公告)号：US11196596B2

公开(公告)日：2021-12-07

申请号：US17018366

申请日：2020-09-11

Applicant: Texas Instruments Incorporated

Inventor： Nikolaus Klemmer ,  Amneh Mohammed Akour ,  Abhijit Anant Patki ,  Timothy Patrick Pauletti ,  Tarkesh Pande

IPC: H04L27/06 ,  H04B1/69 ,  H04L27/14

Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

公开(公告)号：US10651870B2

公开(公告)日：2020-05-12

申请号：US16141671

申请日：2018-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkatesh Srinivasan ,  Kun Shi ,  Victoria Wang ,  Nikolaus Klemmer

IPC: H03M3/00 ,  H03K5/159 ,  H03M1/00 ,  H03M1/16

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

公开(公告)号：US10511467B2

公开(公告)日：2019-12-17

申请号：US15408399

申请日：2017-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Petteri Matti Litmanen ,  Nikolaus Klemmer

IPC: H04L27/00 ,  H03H17/08 ,  H03H11/20 ,  H03B19/14 ,  H03B27/00 ,  H04B1/30 ,  H03L7/099 ,  H03B5/24 ,  H03M1/66 ,  H03K5/156

Abstract: An oscillator architecture with pulse-edge tuning to control the pulse rising and falling edges (such as for duty cycle correction), including a signal generator with a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Pulse-edge tuning circuitry includes a high-side tuning PMOS transistor between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs to provide tuning control signals to the tuning FETs. In an example application, the oscillator design is adapted for a direct conversion RF signal chain (TX and/or RX) including an I-Path and a Q-Path: the signal generator generates ±I and ±Q differential signal frequencies.

公开(公告)号：US10218338B1

公开(公告)日：2019-02-26

申请号：US15782200

申请日：2017-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nikolaus Klemmer ,  Chan Fernando ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Hamid Safiri ,  Atul Kumar Jain

IPC: H03K3/84 ,  H03K5/1252 ,  H03K17/16

Abstract: Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).

公开(公告)号：US10084473B2

公开(公告)日：2018-09-25

申请号：US15455971

申请日：2017-03-10

Applicant: Texas Instruments Incorporated

Inventor： Venkatesh Srinivasan ,  Kun Shi ,  Victoria Wang ,  Nikolaus Klemmer

IPC: H03M3/00 ,  H03M1/00 ,  H03K5/159

CPC classification number: H03M3/38 ,  H03K5/159 ,  H03M1/001 ,  H03M1/164 ,  H03M3/37 ,  H03M3/386 ,  H03M3/464

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

公开(公告)号：US20180025098A1

公开(公告)日：2018-01-25

申请号：US15676632

申请日：2017-08-14

Applicant: Texas Instruments Incorporated

Inventor： Himanshu Arora ,  Siraj Akhtar ,  Nikolaus Klemmer

IPC: G06F17/50 ,  H03B5/12 ,  H03K3/013

CPC classification number: G06F17/50 ,  G06F17/505 ,  G06F17/5063 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B2200/009 ,  H03K3/013

Abstract: A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output node; and at least one cross-coupled switching circuit portion, each cross-coupled switching circuit portion comprising a first transistor having a drain connected to the first output node and a second transistor having a drain connected to the second output node, the first transistor having a gate connected between the drain of the second transistor and the second output node and the second transistor having a gate connected between the drain of the first transistor and the first output node, each of the first and second transistors having a threshold voltage that is determined to be the highest threshold voltage available for the process used to create the VCO.

公开(公告)号：US09806610B2

公开(公告)日：2017-10-31

申请号：US14871140

申请日：2015-09-30

Applicant: Texas Instruments Incorporated

Inventor： Rahmi Hezar ,  Nikolaus Klemmer

IPC: H02M3/156 ,  H02M1/44

CPC classification number: H02M3/156 ,  H02M1/44

Abstract: Noise-shaped frequency hopping power converters are disclosed. An example noise-shaped frequency hopping power converter comprises a shaped number generator having a first output to output a noise-shaped selection signal and a power converter having a first input to receive an input voltage signal, a second input to receive a switching signal that is based on the noise-shaped selection signal, and a second output to output an output voltage signal based on the switching signal.

公开(公告)号：US09413300B2

公开(公告)日：2016-08-09

申请号：US14815619

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Satish V. Uppathil ,  Nikolaus Klemmer ,  Fikret Dulger

IPC: H03F1/22 ,  H04B1/10 ,  H04L27/38 ,  H03F3/195 ,  H03F3/45

CPC classification number: H03F1/223 ,  H03F3/195 ,  H03F3/45179 ,  H03F3/45242 ,  H03F2200/72 ,  H03F2200/75 ,  H03F2203/45024 ,  H03F2203/45306 ,  H03F2203/45392 ,  H03F2203/45481 ,  H03F2203/45631 ,  H04L27/3809

Abstract: A front-end receiver includes an amplifier that has a steady gain over a wide frequency range. The disclosed amplifier adopts an architecture in which a common-source (CS) circuit stacks against a common-gate (CG) circuit. The CG circuit provides the input impedance matching while the CS circuit boosts the amplification gain. As a result, the disclosed amplifier allows the front-end receiver to break free from a tradeoff between input impedance matching and gain boosting. Moreover, the disclosed amplifier achieves power saving and noise reduction by having the CS circuit to share the same bias current with the CG circuit.

Abstract translation: 前端接收机包括在宽频率范围内具有稳定增益的放大器。 所公开的放大器采用其中公共源（CS）电路堆叠到共栅（CG）电路的架构。 当CS电路提高放大增益时，CG电路提供输入阻抗匹配。 结果，所公开的放大器允许前端接收器摆脱输入阻抗匹配和增益提升之间的折中。 此外，所公开的放大器通过使CS电路与CG电路共享相同的偏置电流而实现功率节省和噪声降低。

公开(公告)号：US20160050035A1

公开(公告)日：2016-02-18

申请号：US14824062

申请日：2015-08-11

Applicant: Texas Instruments Incorporated

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer

IPC: H04B17/21 ,  H04B17/318 ,  H04B17/23

CPC classification number: H04B17/21 ,  H04B17/23 ,  H04B17/318

Abstract: A signal profiler generates and monitors a signal profile corresponding to signal power (absolute or relative) per frequency band. The signal profiler includes a signal profile generator and a signal profile monitor. The signal profile generator processes a received signal in pre-defined frequency bands, and captures frequency-band signal power information into frequency bins, this frequency-binned signal power information constituting a signal profile. The signal profile monitor monitors the signal profile, including variations in the signal profile based on pre-defined criteria, and output corresponding profile-variation information (such as flags or interrupt requests). The signal profile generator is an FFT engine. The signal profile monitor is an FSM (finite state machine). An example application is use in a direct conversion wireless receiver to monitor relative image channel power as a signal profile variation that can be used to invoke QMC compensation/configuration.

Abstract translation: 信号剖析器产生并监视与每个频带的信号功率（绝对或相对）相对应的信号轮廓。 信号轮廓仪包括信号轮廓发生器和信号轮廓监视器。 信号分布发生器处理预定义频带中的接收信号，并将频带信号功率信息捕获到频率仓中，该频率合成信号功率信息构成信号分布。 信号配置文件监视器监视信号配置文件，包括基于预定义标准的信号配置文件的变化，并输出相应的配置文件变化信息（如标志或中断请求）。 信号分布生成器是FFT引擎。 信号轮廓监视器是FSM（有限状态机）。 示例应用在直接转换无线接收机中用于监视相对图像信道功率，作为可用于调用QMC补偿/配置的信号轮廓变化。

公开(公告)号：US20160043768A1

公开(公告)日：2016-02-11

申请号：US14811618

申请日：2015-07-28

Applicant: Texas Instruments Incorporated

Inventor： Satish V. Uppathil ,  Nikolaus Klemmer ,  Fikret Dulger

IPC: H04B1/525 ,  H04L27/148 ,  H04B7/04

CPC classification number: H04L27/148 ,  H04B1/0082

Abstract: A front-end receiver includes a first mixer of a first channel, a second mixer of a second channel, and a switching circuit that is configured to select the first mixer or the second mixer during a particular time period. Upon being selected, one of the first mixer or the second mixer is configured to deliver a down-converted signal that down-converts a respective RF signal of either the first or second reception channel. As the tasks of down-conversion and multiplexing are combined at the mixer level, the first and second reception channels may share a baseband circuit while being able to provide a well-balanced metrics of channel isolation, low noise figure, and linearity.

Abstract translation: 前端接收机包括第一通道的第一混频器，第二通道的第二混频器以及被配置为在特定时间段期间选择第一混频器或第二混频器的开关电路。 在被选择时，第一混频器或第二混频器中的一个被配置为传送降频转换的信号，其降低转换第一或第二接收信道的相应RF信号。 随着下变频和多路复用的任务在混频器级别被组合，第一和第二接收信道可以共享基带电路，同时能够提供信道隔离，低噪声系数和线性度的良好平衡度量。