公开(公告)号：US11557722B2

公开(公告)日：2023-01-17

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  G01R33/07 ,  G01R15/20 ,  H01L43/06 ,  H01L23/495 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US11545420B2

公开(公告)日：2023-01-03

申请号：US16787327

申请日：2020-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Liang Wan ,  William Todd Harrison ,  Manu Joseph Prakuzhy ,  Rajen Manicon Murugan

IPC: H01L23/495 ,  H02M3/158 ,  H01L23/00

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

公开(公告)号：US20220285293A1

公开(公告)日：2022-09-08

申请号：US17752037

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20200066716A1

公开(公告)日：2020-02-27

申请号：US16667051

申请日：2019-10-29

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Makarand Ramkrishna Kulkarni

IPC: H01L27/07 ,  H01L23/31 ,  H05K1/02 ,  H01L23/00 ,  H01L23/522

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

公开(公告)号：US20250140708A1

公开(公告)日：2025-05-01

申请号：US18987433

申请日：2024-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

公开(公告)号：US12148556B2

公开(公告)日：2024-11-19

申请号：US17383878

申请日：2021-07-23

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Jonathan Almeria Noquil

IPC: H01L23/498 ,  H01F17/00 ,  H01F27/28 ,  H01F41/04 ,  H01L21/56 ,  H01L23/495 ,  H01L23/522 ,  H05K1/16

Abstract: An electronic device includes a multilevel package substrate, conductive leads, a die, and a package structure. The multilevel package substrate has a first level, a second level, and a third level, each having patterned conductive features and molded dielectric features. The first level includes a first patterned conductive feature with multiple turns that form a first winding. The second level includes a second patterned conductive feature, and the third level includes a third patterned conductive feature with multiple turns that form a second winding. A first terminal of the die is coupled to the first end of the first winding, a second terminal of the die is coupled to the second end of the first winding, and a third terminal of the die is coupled to a first conductive lead. The package structure encloses the first die, the second die, and a portion of the multilevel package substrate.

公开(公告)号：US12040265B2

公开(公告)日：2024-07-16

申请号：US17387794

申请日：2021-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Li Jiang

IPC: H01L23/498 ,  H01L23/13 ,  H01P3/02 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49822 ,  H01P3/02 ,  H05K1/0243

Abstract: In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.

公开(公告)号：US20240178155A1

公开(公告)日：2024-05-30

申请号：US18071972

申请日：2022-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Chittranjan Mohan Gupta ,  Rajen Manicon Murugan ,  Jie Chen

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4839 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/3025

Abstract: An electronic device includes a multilevel package substrate having a first level, a second level, a third level, a conductive signal trace that extends in the second level, and a conductive box shield that surrounds a portion of the conductive signal trace. The electronic device includes a semiconductor die attached to the multilevel package substrate and having a conductive structure coupled to an end of the conductive signal trace. The electronic device includes a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.

公开(公告)号：US11955479B2

公开(公告)日：2024-04-09

申请号：US16667051

申请日：2019-10-29

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Makarand Ramkrishna Kulkarni

IPC: H01L27/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H05K1/02

CPC classification number: H01L27/0733 ,  H01L23/3128 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H05K1/0231 ,  H01L2924/15311 ,  H05K2201/09118

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

公开(公告)号：US20230352315A1

公开(公告)日：2023-11-02

申请号：US17733921

申请日：2022-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L21/486 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L24/16

Abstract: One example includes a method for fabricating a substrate-integrated waveguide (SIW). The method includes forming a first metal layer on a carrier surface. The first metal layer can extend along an axis. The method also includes forming a first metal sidewall extending from a first edge of the first metal layer along the axis and forming a second metal sidewall extending from a second edge of the first metal layer opposite the first edge along the axis to form a trough extending along the axis. The method also includes providing a dielectric material over the first metal layer and over the first and second metal sidewalls. The method further includes forming a second metal layer over the dielectric material and over the first and second metal sidewalls. The second metal layer can extend along the axis to enclose the SIW in all radial directions along the axis.