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    CHARGE PUMP
    32.
    发明申请
    CHARGE PUMP 有权

    公开(公告)号：US20210376838A1

    公开(公告)日：2021-12-02

    申请号：US17397954

    申请日：2021-08-09

    Applicant: Texas Instruments Incorporated

    Inventor： Salvatore Luciano Finocchiaro ,  Tolga Dinc ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

    IPC: H03L7/089 ,  H02M3/07 ,  H03L7/087

    Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

    Baluns for RF signal conversion and impedance matching
    33.
    发明授权
    Baluns for RF signal conversion and impedance matching 有权

    公开(公告)号：US10461717B2

    公开(公告)日：2019-10-29

    申请号：US16246643

    申请日：2019-01-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Siraj Akhtar ,  Richard Francis Taylor ,  Petteri Litmanen

    IPC: H01L23/522 ,  H03H7/42 ,  H01L23/64 ,  H01L23/66 ,  H01L49/02 ,  H01F21/12 ,  H01F27/28 ,  H01F27/29 ,  H01F41/04

    Abstract: In described examples of a magnetically coupled structure on a substrate with an integrated circuit device, the structure includes a first coil in a differential configuration, a second coil located above the first coil in a generally stacked configuration, and a center tap connection to a winding of the second coil. The first coil includes a first differential terminal, a second differential terminal, and metal windings of the first coil. The first coil's metal windings form a continuous spiral electrical path between the first and second differential terminals. The first coil's metal windings include turns and crossing connections between the turns. The turns are fabricated in an integrated circuit metal wiring level, and the crossing connections are fabricated in at least one metal level other than the metal wiring level containing the turns. The center tap is positioned to create a balanced structure.

    PLL lock range extension over temperature
    35.
    发明授权
    PLL lock range extension over temperature 有权

    公开(公告)号：US10187071B2

    公开(公告)日：2019-01-22

    申请号：US15387636

    申请日：2016-12-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Himanshu Arora ,  Siraj Akhtar ,  Lu Sun ,  Hamid Safiri ,  Wenjing Lu ,  Nikolaus Klemmer

    IPC: H03L7/099 ,  H03L7/10 ,  H03L1/02

    Abstract: A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

    D LATCH CIRCUIT
    38.
    发明申请
    D LATCH CIRCUIT 审中-公开

    公开(公告)号：US20170207774A1

    公开(公告)日：2017-07-20

    申请号：US15408412

    申请日：2017-01-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Diptendu Ghosh ,  Petteri Matti Litmanen ,  Siraj Akhtar

    IPC: H03K5/00 ,  H03K3/356

    CPC classification number: H03K5/00006 ,  H03K3/356139

    Abstract: A latch circuit includes first and second inverters, each with latching (inner) and clocking (outer) PMOS/NMOS transistor pairs in a series/stack configuration. A first inverter includes a D_latching PMOS/NMOS transistor pair, drain-connected at a D node. A first /clock PMOS transistor is coupled between a high rail and a source terminal of the D_latching PMOS transistor, and a first clock NMOS transistor is coupled between a low rail and the source terminal of the D_latching NMOS transistor. A second inverter includes a Dbar_latching PMOS/NMOS transistor pair, drain-connected at a Dbar node. A second /clock PMOS transistor is coupled between the high rail and the source terminal of the Dbar_latching PMOS transistor, and a second clock NMOS transistor is coupled between the low rail and the Dbar_latching NMOS transistor. A cross-coupling switch circuit connected between the D node and the Dbar node. The first and second /clock PMOS transistors can be combined as a single /clock PMOS transistor connected between the high rail and the source terminals of respectively the D_latching and Dbar_latching PMOS transistors, and the first and second clock NMOS transistors can be combined as a single clock NMOS transistor connected between the low rail and the source terminals of respectively the D_latching and Dbar_latching NMOS transistors. As an example application, the latch circuit can be used in a quadrature (IQ) frequency divider.

    Method and Apparatus Having Enhanced Oscillator Phase Noise Using High Vt MOS Devices
    39.
    发明申请
    Method and Apparatus Having Enhanced Oscillator Phase Noise Using High Vt MOS Devices 有权
    使用高Vt MOS器件增强振荡器相位噪声的方法和装置

    公开(公告)号：US20150333698A1

    公开(公告)日：2015-11-19

    申请号：US14712336

    申请日：2015-05-14

    Applicant: Texas Instruments Incorporated

    Inventor： Himanshu Arora ,  Siraj Akhtar ,  Nikolaus Klemmer

    IPC: H03B5/12 ,  G06F17/50 ,  H03K3/013

    CPC classification number: G06F17/50 ,  G06F17/505 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B2200/009 ,  H03K3/013

    Abstract: A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output node; and at least one cross-coupled switching circuit portion, each cross-coupled switching circuit portion comprising a first transistor having a drain connected to the first output node and a second transistor having a drain connected to the second output node, the first transistor having a gate connected between the drain of the second transistor and the second output node and the second transistor having a gate connected between the drain of the first transistor and the first output node, each of the first and second transistors having a threshold voltage that is determined to be the highest threshold voltage available for the process used to create the VCO.

    Abstract translation: 压控振荡器（VCO）包括连接以接收输入电压并具有第一输出节点和第二输出节点的谐振器电路; 和至少一个交叉耦合开关电路部分，每个交叉耦合的开关电路部分包括具有连接到第一输出节点的漏极的第一晶体管和连接到第二输出节点的漏极的第二晶体管，第一晶体管具有 连接在第二晶体管的漏极和第二输出节点之间的栅极，第二晶体管具有连接在第一晶体管的漏极和第一输出节点之间的栅极，第一和第二晶体管中的每一个具有阈值电压，其被确定为 是可用于创建VCO的过程的最高阈值电压。

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