公开(公告)号：US09904645B2

公开(公告)日：2018-02-27

申请号：US14530203

申请日：2014-10-31

Applicant: Texas Instruments Incorporated

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/364 ,  H04L12/819 ,  H04L12/801

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

公开(公告)号：US20160124883A1

公开(公告)日：2016-05-05

申请号：US14530203

申请日：2014-10-31

Applicant: Texas Instruments Incorporated

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

Abstract translation: 本发明是总线通信协议。 主设备存储总线信用。 主设备只有在拥有足够数量和类型的总线信用时才可以传输总线事务。 在传输时，主设备减少存储的总线信用的数量。 总线信用量对应于从设备上用于接收总线事务的资源。 如果伴随着适当的信用，从设备必须接收总线交易。 从设备为事务提供服务。 然后从设备传送信用回报。 主设备将相应的信用数量和类型添加到存储量。 从设备准备接受另一个总线事务，并且主设备被重新启用以启动总线事务。 在许多类型的交互中，根据进程的状态，总线代理可以充当主机和从机。

公开(公告)号：US11803505B2

公开(公告)日：2023-10-31

申请号：US17735255

申请日：2022-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/42 ,  G06F13/362

CPC classification number: G06F13/4252 ,  G06F13/362

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

公开(公告)号：US11212256B2

公开(公告)日：2021-12-28

申请号：US16786734

申请日：2020-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

IPC: H04L29/06

Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

公开(公告)号：US11099933B2

公开(公告)日：2021-08-24

申请号：US16808683

申请日：2020-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/312 ,  G06F11/07 ,  G06F12/08 ,  G06F11/10 ,  G06F11/14 ,  G06F9/345 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F13/38 ,  G06F13/40

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US20200285474A1

公开(公告)日：2020-09-10

申请号：US16825383

申请日：2020-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/345 ,  G06F11/00 ,  G06F12/02

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US10606598B2

公开(公告)日：2020-03-31

申请号：US16139858

申请日：2018-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/312 ,  G06F9/34 ,  G06F11/00 ,  G06F12/02 ,  G06F13/18 ,  G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/345 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US20190220277A1

公开(公告)日：2019-07-18

申请号：US16361449

申请日：2019-03-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

公开(公告)号：US20190058691A1

公开(公告)日：2019-02-21

申请号：US15679307

申请日：2017-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

IPC: H04L29/06

CPC classification number: H04L63/0218 ,  H04L63/0236 ,  H04L63/0245

Abstract: A flexible hybrid firewall architecture that allows a mix of firewalls at end points in front of a target and at the initiator points. Groups of Priv-IDs may be created where each group is isolated from other worlds, with all firewalls controlled by a device management and security module.

公开(公告)号：US10078551B2

公开(公告)日：2018-09-18

申请号：US15384355

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/00 ,  G06F9/312 ,  G06F13/36 ,  G06F12/00 ,  G06F11/10 ,  G06F11/14 ,  G06F9/38 ,  G06F13/38 ,  G06F9/345 ,  G06F9/30 ,  G06F13/40 ,  G06F12/0817

CPC classification number: G06F11/1076 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30141 ,  G06F9/345 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3881 ,  G06F9/3891 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1405 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/38 ,  G06F13/40 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.