公开(公告)号：US11101344B2

公开(公告)日：2021-08-24

申请号：US16595100

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US10685885B2

公开(公告)日：2020-06-16

申请号：US15943671

申请日：2018-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

公开(公告)号：US10461169B2

公开(公告)日：2019-10-29

申请号：US15911884

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei Yeh ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/285 ,  H01L23/485

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.

公开(公告)号：US09935013B2

公开(公告)日：2018-04-03

申请号：US14248755

申请日：2014-04-09

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0607 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621

Abstract: A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device.

公开(公告)号：US09842768B2

公开(公告)日：2017-12-12

申请号：US15489947

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Cheng Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.

公开(公告)号：US09564332B2

公开(公告)日：2017-02-07

申请号：US14037881

申请日：2013-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wen-Jia Hsieh ,  Chih-Lin Wang ,  Chia-Der Chang

IPC: H01L21/28 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/265 ,  H01L29/165 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02244 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括形成在半导体衬底上的半导体衬底和金属栅极叠层。 半导体器件还包括形成在半导体衬底上并围绕金属栅堆叠的绝缘层，其中金属栅叠层包括金属栅电极。 半导体器件还包括形成在绝缘层上并与绝缘层直接接触的金属氧化物结构。 金属氧化物结构包括金属栅电极的氧化材料。

公开(公告)号：US09136356B2

公开(公告)日：2015-09-15

申请号：US14176873

申请日：2014-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chih Lin ,  Long-Jie Hong ,  Chih-Lin Wang ,  Chia-Der Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成两个隔离结构以在衬底中的两个隔离结构之间限定翅片结构。 形成虚拟栅极和间隔物，桥接两个隔离结构和鳍状结构。 用伪栅极和间隔物作为掩模蚀刻两个隔离结构，以在两个隔离结构中的间隔物下方形成多个斜面。 在多个斜面上形成栅极蚀刻停止层。 去除虚拟栅极和虚拟栅极之下的两个隔离结构以产生由间隔物和栅极蚀刻停止层限制的空腔。 然后在空腔中形成栅极。

公开(公告)号：US20240379740A1

公开(公告)日：2024-11-14

申请号：US18781290

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US11963460B2

公开(公告)日：2024-04-16

申请号：US17839326

申请日：2022-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang Tseng ,  Chih-Lin Wang ,  Yi-Huang Wu

IPC: H10N50/10 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/10 ,  H10N50/01 ,  H10N50/80

Abstract: A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.

公开(公告)号：US11694924B2

公开(公告)日：2023-07-04

申请号：US17365911

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L23/485 ,  H01L21/8238 ,  H01L29/165 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/76814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.