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公开(公告)号:US20230263074A1
公开(公告)日:2023-08-17
申请号:US17747757
申请日:2022-05-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: MingYuan Song , Chien-Min Lee , Xinyu Bao
CPC classification number: H01L43/04 , H01L27/222 , H01L43/06 , H01L43/10 , H01L43/14
Abstract: A magnetic memory device including bottom electrode bridges and a spin-orbit torque structure overlapping and physically coupled to the bottom electrode bridges and a method of forming the same are disclosed. In an embodiment, a memory includes a first electrode on a first via; a second electrode on a second via; a spin-orbit torque (SOT) structure physically and electrically coupled to the first electrode and the second electrode, the SOT structure overlapping the first electrode and the second electrode; and a magnetic tunnel junction (MTJ) on the SOT structure.
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公开(公告)号:US11683988B2
公开(公告)日:2023-06-20
申请号:US17221674
申请日:2021-04-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Sheng-Chih Lai , Han-Ting Tsai , Chung-Te Lin
IPC: H10N50/01 , H10B61/00 , G11C11/16 , H10N50/10 , H10N50/80 , H01L43/12 , H01L27/22 , H01L43/08 , H01L43/02
CPC classification number: H01L43/12 , G11C11/161 , H01L27/226 , H01L43/02 , H01L43/08
Abstract: A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.
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公开(公告)号:US11588107B2
公开(公告)日:2023-02-21
申请号:US17369671
申请日:2021-07-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Han-Ting Tsai , Jyu-Horng Shieh , Chung-Te Lin
Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.
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公开(公告)号:US20220216396A1
公开(公告)日:2022-07-07
申请号:US17518789
申请日:2021-11-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yen-Lin Huang , MingYuan Song , Chien-Min Lee , Shy-Jay Lin , Chi-Feng Pai , Chen-Yu Hu , Chao-Chung Huang , Kuan-Hao Chen , Chia-Chin Tsai , Yu-Fang Chiu , Cheng-Wei Peng
Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.
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公开(公告)号:US11189658B2
公开(公告)日:2021-11-30
申请号:US15966639
申请日:2018-04-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Hui-Hsien Wei , Chung-Te Lin , Han-Ting Tsai , Tai-Yen Peng , Pin-Ren Dai , Chien-Min Lee , Sheng-Chih Lai , Wei-Chih Wen
Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.
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公开(公告)号:US20210367143A1
公开(公告)日:2021-11-25
申请号:US17145048
申请日:2021-01-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-Min Lee , Shy-Jay Lin
Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.
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37.
公开(公告)号:US11088201B2
公开(公告)日:2021-08-10
申请号:US16372792
申请日:2019-04-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tsann Lin , Chien-Min Lee , Ji-Feng Ying
Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
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公开(公告)号:US20210134339A1
公开(公告)日:2021-05-06
申请号:US17002351
申请日:2020-08-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: MingYuan Song , Shy-Jay Lin , Chien-Min Lee , William Joseph Gallagher
Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.
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39.
公开(公告)号:US20200006425A1
公开(公告)日:2020-01-02
申请号:US16372792
申请日:2019-04-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tsann Lin , Chien-Min Lee , Ji-Feng Ying
Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
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