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公开(公告)号:US11062968B2
公开(公告)日:2021-07-13
申请号:US16548165
申请日:2019-08-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Hao Chen , Chih-Chien Pan , Li-Hui Cheng , Chin-Fu Kao , Szu-Wei Lu
IPC: H01L23/18 , H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00
Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.
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公开(公告)号:US20210202455A1
公开(公告)日:2021-07-01
申请号:US16925326
申请日:2020-07-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tsung-Fu Tsai , Chin-Fu Kao , Pu Wang , Szu-Wei Lu
Abstract: A package structure includes a circuits substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.
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公开(公告)号:US11031381B2
公开(公告)日:2021-06-08
申请号:US16198858
申请日:2018-11-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Hao Chen , Chin-Fu Kao , Li-Hui Cheng , Szu-Wei Lu
Abstract: An optical transceiver including a photonic integrated circuit component, an electric integrated circuit component and an insulating encapsulant is provided. The photonic integrated circuit component includes at least one optical input/output portion and at least one groove located in proximity of the at least one optical input/output portion. The electric integrated circuit component is disposed on and electrically connected to the photonic integrated circuit component.
The insulating encapsulant is disposed on the photonic integrated circuit component and laterally encapsulating the electric integrated circuit component. The at least one groove of the photonic integrated circuit component is revealed by the insulating encapsulant and is adapted for insertion of a photonic device.-
公开(公告)号:US20200135601A1
公开(公告)日:2020-04-30
申请号:US16172836
申请日:2018-10-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Ping-Yin Hsieh , Chin-Fu Kao , Li-Hui Cheng , Szu-Wei Lu
Abstract: A package structure includes a plurality of first dies, a first encapsulant, and a first redistribution structure. The first encapsulant encapsulates the first dies. The first redistribution structure is disposed on the first dies and the first encapsulant. The first redistribution structure includes a dielectric layer covering a top surface and sidewalls of the first encapsulant.
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公开(公告)号:US10522470B1
公开(公告)日:2019-12-31
申请号:US16035693
申请日:2018-07-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jung-Hua Chang , Chin-Fu Kao
IPC: H01L21/768 , H01L23/522 , H01L23/538 , H01L23/00 , H01L21/56
Abstract: A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.
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公开(公告)号:US12294002B2
公开(公告)日:2025-05-06
申请号:US18664483
申请日:2024-05-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Yun Hou , Sung-Hui Huang , Kuan-Yu Huang , Hsien-Pin Hu , Yushun Lin , Heh-Chang Huang , Hsing-Kuo Hsia , Chih-Chieh Hung , Ying-Ching Shih , Chin-Fu Kao , Wen-Hsin Wei , Li-Chung Kuo , Chi-Hsi Wu , Chen-Hua Yu
IPC: H01L25/00 , H01L21/48 , H01L23/24 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
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公开(公告)号:US20240258266A1
公开(公告)日:2024-08-01
申请号:US18629670
申请日:2024-04-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kai Jun Zhan , Chin-Fu Kao , Kuang-Chun Lee , Ming-Da Cheng , Chen-Shien Chen
IPC: H01L23/00
CPC classification number: H01L24/81 , H01L24/16 , H01L2224/16058 , H01L2224/16227 , H01L2224/81024 , H01L2224/81193 , H01L2224/81203
Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.
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公开(公告)号:US11901255B2
公开(公告)日:2024-02-13
申请号:US17869003
申请日:2022-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Chien Pan , Chin-Fu Kao , Li-Hui Cheng , Szu-Wei Lu
IPC: H01L23/31 , H01L25/065 , H01L23/498 , H01L21/48 , H01L21/56 , H01L21/768 , H01L23/00
CPC classification number: H01L23/3157 , H01L21/4853 , H01L21/4857 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/76898 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L24/81 , H01L24/96 , H01L24/97 , H01L25/0657
Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.
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公开(公告)号:US11476219B2
公开(公告)日:2022-10-18
申请号:US17026983
申请日:2020-09-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jung-Hua Chang , Jian-Yang He , Chin-Fu Kao
Abstract: A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.
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公开(公告)号:US11456268B2
公开(公告)日:2022-09-27
申请号:US16252734
申请日:2019-01-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jung-Hua Chang , Chin-Fu Kao
Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.
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