公开(公告)号：US09607809B2

公开(公告)日：2017-03-28

申请号：US14207468

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ching Lo ,  Po-Hsiung Leu ,  Tzu-Chun Lin ,  Ding-I Liu ,  Jen-Chi Chang ,  Ho-Ta Chuang

IPC: C23C16/00 ,  H01J37/32 ,  C23C16/507

CPC classification number: H01J37/321 ,  C23C16/507 ,  H01J37/3211

Abstract: A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator.

公开(公告)号：US08946095B2

公开(公告)日：2015-02-03

申请号：US13660363

申请日：2012-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li Chen ,  Jyh-Nan Lin ,  Chin-Feng Sun ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L21/469 ,  H01L21/283

CPC classification number: H01L21/283 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02214 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/76801

Abstract: A method of forming an interlayer dielectric film above a metal gate of a metal oxide semiconductor device comprises forming a metal gate above a semiconductor substrate; and forming the interlayer dielectric film above the metal gate by reacting a silicon-containing compound as precursor and a reactant for oxidizing the silicon-containing compound. The silicon-containing compound has the formula: Six(A)y(B)z(C)m(D)n  (I) wherein x is in the range of from 1 to 9; y+z+m+n is in the range of from 4 to 20; and A, B, C, and D independently represent a functional group connecting with a silicon atom. The functional group is selected from a group consisting of alkyl, alkenyl, alkynyl, aryl, alkylaryl, alkoxyl, alkylcarbonyl, carboxyl, alkylcarbonyloxy, amide, amino, alkylcarbonylamino, —NO2, and —CN.

Abstract translation: 在金属氧化物半导体器件的金属栅极上形成层间电介质膜的方法包括在半导体衬底上形成金属栅极; 以及通过使含硅化合物作为前体和用于氧化含硅化合物的反应物反应，在金属栅上方形成层间电介质膜。 含硅化合物具有下式：其中x在1至9的范围内的六（A）y（B）z（C）m（D）n（I） y + z + m + n在4至20的范围内; A，B，C和D独立地表示与硅原子连接的官能团。 官能团选自烷基，烯基，炔基，芳基，烷基芳基，烷氧基，烷基羰基，羧基，烷基羰基氧基，酰胺，氨基，烷基羰基氨基，-NO 2和-CN。

公开(公告)号：US11742393B2

公开(公告)日：2023-08-29

申请号：US17683749

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L29/26 ,  H01L21/02172 ,  H01L21/02436 ,  H01L21/7685 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L23/53295

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US20220190122A1

公开(公告)日：2022-06-16

申请号：US17683749

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan LIN ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US11315829B2

公开(公告)日：2022-04-26

申请号：US16890413

申请日：2020-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-Nan Lin ,  Chia-Yu Wu ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522 ,  C23F1/12

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

公开(公告)号：US20200090986A1

公开(公告)日：2020-03-19

申请号：US16550901

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhy-nan Lin ,  Mu-Min Hung ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  C23C16/34 ,  C23C16/455

Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.

公开(公告)号：US10395918B2

公开(公告)日：2019-08-27

申请号：US14836574

申请日：2015-08-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Tsung Wu ,  Po-Hsiung Leu ,  Ding-I Liu ,  Si-Wen Liao ,  Hsiang-Sheng Kung

IPC: H01J37/32 ,  H01L21/02

Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.

公开(公告)号：US20190006474A1

公开(公告)日：2019-01-03

申请号：US16009925

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US10161041B2

公开(公告)日：2018-12-25

申请号：US15221506

申请日：2016-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Chan Lo ,  Yi-Fang Lai ,  Po-Hsiung Leu ,  Ding-I Liu ,  Si-Wen Liao ,  Kai-Shiung Hsu ,  Jheng-Uei Hsieh ,  Shian-Huei Lin ,  Jui-Fu Hsu ,  Cheng-Tsung Wu

IPC: C23C16/46 ,  C23C16/458

Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.

公开(公告)号：US09831307B2

公开(公告)日：2017-11-28

申请号：US15370244

申请日：2016-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chang Chen ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/76 ,  H01L21/762 ,  H01L29/165

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.