公开(公告)号：US11532507B2

公开(公告)日：2022-12-20

申请号：US17169989

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chung-Ting Ko ,  Jr-Hung Li ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/08

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

公开(公告)号：US11495494B2

公开(公告)日：2022-11-08

申请号：US16688071

申请日：2019-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Yi-Jyun Huang ,  Sheng-Hsiung Wang ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L23/535 ,  H01L29/06 ,  H01L29/78

Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.

公开(公告)号：US20220310398A1

公开(公告)日：2022-09-29

申请号：US17335502

申请日：2021-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Ping Lin ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/285 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/66

Abstract: A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

公开(公告)号：US20220238702A1

公开(公告)日：2022-07-28

申请号：US17717777

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Heng Wang ,  Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/78

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

公开(公告)号：US20220199530A1

公开(公告)日：2022-06-23

申请号：US17694135

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Chia-Hsien Yao ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

公开(公告)号：US11244832B2

公开(公告)日：2022-02-08

申请号：US16939465

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ying Lin ,  Mei-Yun Wang ,  Hsien-Cheng Wang ,  Fu-Kai Yang ,  Shih-Wen Liu ,  Hsiao-Chiu Hsu

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/033 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.

公开(公告)号：US11152486B2

公开(公告)日：2021-10-19

申请号：US16511258

申请日：2019-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.

公开(公告)号：US20210193806A1

公开(公告)日：2021-06-24

申请号：US17195251

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hung Tsai ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/3205 ,  H01L21/768 ,  H01L29/40 ,  H01L21/3105

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.

公开(公告)号：US11037924B2

公开(公告)日：2021-06-15

申请号：US15867058

申请日：2018-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/4757 ,  H01L21/302 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417 ,  H01L29/165

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.

公开(公告)号：US10685880B2

公开(公告)日：2020-06-16

申请号：US15690709

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Yi-Jyun Huang ,  Sheng-Hsiung Wang ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L23/535 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.