公开(公告)号：US20210391534A1

公开(公告)日：2021-12-16

申请号：US17461132

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US20210376228A1

公开(公告)日：2021-12-02

申请号：US16887244

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Feng Yin ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

公开(公告)号：US11063217B2

公开(公告)日：2021-07-13

申请号：US16983928

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A semiconductor device includes an inter-layer dielectric (ILD) layer, a first metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a second metallization pattern. The first metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer, in which the etch stop layer has a portion extending beyond an edge of the metal-containing compound layer. The memory cell is over the metal-containing compound layer and including a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The second metallization pattern extends through the portion of the etch stop layer to the first metallization pattern.

公开(公告)号：US10971682B2

公开(公告)日：2021-04-06

申请号：US16866101

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

Abstract: A method for fabricating a memory device is provided. The method includes depositing a resistance switching element layer over a bottom electrode layer; depositing a top electrode layer over the resistance switching element layer; etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack; depositing a first spacer layer over the memory stack and; etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack; depositing a second spacer layer over the memory stack and the first spacer; etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and depositing an etch stop layer over and in contact with a top of the second spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.

公开(公告)号：US10395937B2

公开(公告)日：2019-08-27

申请号：US15689334

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Dian-Hau Chen ,  Han-Ting Tsai ,  Tsung-Lin Lee ,  Chia-Cheng Ho ,  Ming-Shiang Lin

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L21/3115

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.

公开(公告)号：US09570613B2

公开(公告)日：2017-02-14

申请号：US14622180

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kai-Hsuan Lee ,  Cheng-Yu Yang ,  Hsiang-Ku Shen ,  Han-Ting Tsai ,  Yimin Huang

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/36 ,  H01L21/02 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/80 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/0223 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/495 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/802

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack over a portion of the fin structure, and the fin structure includes an intermediate portion under the gate stack and upper portions besides the intermediate portion. The semiconductor device structure further includes a contact layer over the fin structure. The contact layer includes a metal material, and the upper portions of the fin structure also include the metal material.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的半导体衬底和鳍状结构。 半导体器件结构还包括在鳍结构的一部分上的栅极堆叠，并且鳍结构包括在栅叠层下方的中间部分和除了中间部分之外的上部。 半导体器件结构还包括在鳍结构上的接触层。 接触层包括金属材料，翅片结构的上部还包括金属材料。