公开(公告)号：US10685896B2

公开(公告)日：2020-06-16

申请号：US15486306

申请日：2017-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/11 ,  H01L23/544 ,  H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/10 ,  H01L23/538

Abstract: An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.

公开(公告)号：US10665545B2

公开(公告)日：2020-05-26

申请号：US16134963

申请日：2018-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Hao Liao ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Meng-Che Tu

IPC: H01L21/00 ,  H01L23/532 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  C08L33/08 ,  C08L79/08 ,  C08L65/00 ,  C08K5/42 ,  H01L23/31

Abstract: Semiconductor devices, semiconductor packages and methods of forming the same are provided. One of the semiconductor device includes a dielectric layer and a connector. The dielectric layer includes a dielectric material and an additive, wherein the additive includes a compound represented by Chemical Formula 1. The connector is disposed in the dielectric layer.

公开(公告)号：US10658287B2

公开(公告)日：2020-05-19

申请号：US15992200

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Hao Liao ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/52 ,  H01L23/31 ,  H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00

Abstract: A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

公开(公告)号：US20200118960A1

公开(公告)日：2020-04-16

申请号：US16714824

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/075 ,  H01L25/07 ,  H01L25/11 ,  H01L25/04 ,  H01L23/538

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die has a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

公开(公告)号：US20200083189A1

公开(公告)日：2020-03-12

申请号：US16413591

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang ,  Yung-Chi Chu ,  Hung-Chun Cho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  C09J165/00

Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.

公开(公告)号：US10529593B2

公开(公告)日：2020-01-07

申请号：US15964092

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/04 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package manufacturing method thereof are provided. The semiconductor package includes a high-power device die, a redistribution structure, a heat dissipation module and a molding compound. The high-power device die has a front side and a back side opposite to the front side. The redistribution structure is disposed at the front side. The heat dissipation module is in direct contact with the back side. The molding compound is disposed between the redistribution structure and the heat dissipation module, and surrounding the high-power device die. The molding compound has a body portion and an extended portion. An interface between the body portion and the heat dissipation module is substantially parallel to the back side of the high-power device die. A thickness of the extended portion is greater than a thickness of the body portion.

公开(公告)号：US20190295884A1

公开(公告)日：2019-09-26

申请号：US16396793

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/538 ,  H01L21/78 ,  H01L21/02 ,  H01L23/532 ,  H01L23/31

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

公开(公告)号：US20190252209A1

公开(公告)日：2019-08-15

申请号：US16396779

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Feng Chen ,  Chih-Hua Chen ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hung-Jui Kuo ,  Hui-Jung Tsai ,  Hao-Yi Tsai

IPC: H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.

公开(公告)号：US20190237423A1

公开(公告)日：2019-08-01

申请号：US15884254

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L23/00 ,  H01L23/29

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat.

公开(公告)号：US10297551B2

公开(公告)日：2019-05-21

申请号：US15235109

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Jung Tsai ,  Hung-Jui Kuo ,  Yun-Chen Hsieh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer. The seed layer and the conductive patterns include a same material. While maintain a substantially uniform pitch width in the conductive pattern, the seed layer exposed by the conductive patterns is selectively removed through a dry etch process to form a plurality of seed layer patterns. The conductive patterns and the seed layer patterns form a plurality of redistribution conductive patterns.