公开(公告)号：US10755968B2

公开(公告)日：2020-08-25

申请号：US16222787

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Shan Chen ,  Chan-Syun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L21/32 ,  H01L21/02

Abstract: A method is provided. A sacrificial layer is formed over a semiconductor substrate. An etching process is performed to form an opening in the sacrificial layer. The etching process includes a first cycle and a second cycle performed after the first cycle, and each of the first cycle and the second cycle includes applying a passivation gas and an etchant gas over the sacrificial layer, and performing an ionized gas bombardment on the sacrificial layer after applying the passivation gas and the etchant gas over the sacrificial layer. The passivation gas is applied at a first flow rate in the first cycle and is applied at a second flow rate in the second cycle, and the first flow rate is higher than the second flow rate.

公开(公告)号：US20200243336A1

公开(公告)日：2020-07-30

申请号：US16258656

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

公开(公告)号：US20200020776A1

公开(公告)日：2020-01-16

申请号：US16504117

申请日：2019-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan Syun David Yang ,  Li-Te Lin

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065

Abstract: A method of forming an air-gap spacer in a semiconductor device includes providing a device including a gate stack, a plurality of spacer layers disposed on a sidewall of the gate stack, and a source/drain feature adjacent to the gate stack. In some embodiments, a first spacer layer of the plurality of spacer layers is removed to form an air gap on the sidewall of the gate stack. In various examples, a first sealing layer is then deposited over a top portion of the air gap to form a sealed air gap, and a second sealing layer is deposited over the first sealing layer. Thereafter, a first self-aligned contact (SAC) layer is etched from over the source/drain feature using a first etching process. In various embodiments, the first etching process selectively etches the first SAC layer while the first and second sealing layers remain unetched.

公开(公告)号：US10535520B2

公开(公告)日：2020-01-14

申请号：US15684282

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yuan Tseng ,  Wei-Liang Lin ,  Li-Te Lin ,  Ru-Gun Liu ,  Min Cao

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.

公开(公告)号：US20200006062A1

公开(公告)日：2020-01-02

申请号：US16259345

申请日：2019-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Han-Yu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/40

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

公开(公告)号：US10032887B2

公开(公告)日：2018-07-24

申请号：US15488814

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L29/66 ,  H01L21/00 ,  H01L21/02 ,  H01L21/04 ,  H01L21/28 ,  H01L29/08

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

公开(公告)号：US20170365691A1

公开(公告)日：2017-12-21

申请号：US15488814

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L29/66 ,  H01L21/04 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66583 ,  H01L21/02642 ,  H01L21/0465 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2224/0348 ,  H01L2224/03916

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

公开(公告)号：US09627258B1

公开(公告)日：2017-04-18

申请号：US15183452

申请日：2016-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3115 ,  H01L23/522 ,  H01L27/11

CPC classification number: H01L29/66583 ,  H01L21/02642 ,  H01L21/0465 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2224/0348 ,  H01L2224/03916

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

公开(公告)号：US11978672B2

公开(公告)日：2024-05-07

申请号：US17885410

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02263 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/823475 ,  H01L23/5226 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.

公开(公告)号：US11908685B2

公开(公告)日：2024-02-20

申请号：US17201744

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Han-Yu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/265

CPC classification number: H01L21/02321 ,  H01L21/26586 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/66545

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.