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    Self-Aligned Etch in Semiconductor Devices
    32.
    发明申请
    Self-Aligned Etch in Semiconductor Devices 有权

    公开(公告)号：US20210335783A1

    公开(公告)日：2021-10-28

    申请号：US16944025

    申请日：2020-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768

    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

    CAPACITANCE REDUCTION BY METAL CUT DESIGN
    33.
    发明申请
    CAPACITANCE REDUCTION BY METAL CUT DESIGN 审中-公开

    公开(公告)号：US20200098631A1

    公开(公告)日：2020-03-26

    申请号：US16531232

    申请日：2019-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Shang-Wen Chang ,  Yi-Hsun Chiu

    IPC: H01L21/768 ,  G06F17/50

    Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

    SEMICONDUCTOR DEVICES INCLUDING DECOUPLING CAPACITORS
    35.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING DECOUPLING CAPACITORS 有权

    公开(公告)号：US20250105138A1

    公开(公告)日：2025-03-27

    申请号：US18977704

    申请日：2024-12-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

    IPC: H01L23/522 ,  G11C11/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12 ,  H01L27/146

    Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

    Backside PN junction diode
    36.
    发明授权
    Backside PN junction diode 有权

    公开(公告)号：US12183736B2

    公开(公告)日：2024-12-31

    申请号：US18356802

    申请日：2023-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

    IPC: H01L27/088 ,  H01L27/07 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

    Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

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