公开(公告)号：US20060273330A1

公开(公告)日：2006-12-07

申请号：US11498774

申请日：2006-08-04

申请人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

IPC分类号： H01L33/00

CPC分类号： H01L27/10894 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region of the semiconductor substrate in a depth direction, and burying a second semiconductor region in the region from which part of the semiconductor substrate has been removed in the depth direction.

摘要翻译： 一种半导体器件制造方法，包括：选择性地去除SOI衬底中的一部分掩埋氧化物层和第一半导体层，所述SOI衬底具有形成于半导体衬底上方的所述掩埋氧化物层的第一半导体层，并且暴露所述半导体衬底的一部分， 区域，并且在半导体衬底的一部分已经在深度方向上被去除的区域中埋入第二半导体区域。

公开(公告)号：US20060258076A1

公开(公告)日：2006-11-16

申请号：US11399655

申请日：2006-04-07

申请人： Ichiro Mizushima ,  Hajime Nagano ,  Yoshio Ozawa ,  Hisataka Meguro ,  Takashi Suzuki

发明人： Ichiro Mizushima ,  Hajime Nagano ,  Yoshio Ozawa ,  Hisataka Meguro ,  Takashi Suzuki

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11521

摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.

摘要翻译： 在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

公开(公告)号：US20060157697A1

公开(公告)日：2006-07-20

申请号：US11232851

申请日：2005-09-23

申请人： Hajime Nagano

发明人： Hajime Nagano

IPC分类号： H01L21/66 ,  H01L23/58 ,  G01R31/26

CPC分类号： H01L22/20 ,  H01L2224/16 ,  H01L2924/01057 ,  H01L2924/01067

摘要： A system for adjusting a manufacturing condition of an electronic device includes: an inspection tool configured to inspect a plurality of protrusions on a substance layer for manufacturing an electronic device; a height calculation unit configured to calculate each of heights of the protrusions, based on the inspection result; and an adjustment unit configured to adjust a manufacturing condition of the electronic device in order to remove the protrusions, based on the heights.

摘要翻译： 一种用于调整电子设备的制造条件的系统，包括：检查工具，被配置为检查用于制造电子设备的物质层上的多个突起; 高度计算单元，被配置为基于检查结果计算突起的高度; 以及调整单元，被配置为基于高度来调整电子设备的制造条件以便去除突起。

公开(公告)号：US20060131696A1

公开(公告)日：2006-06-22

申请号：US11350027

申请日：2006-02-09

申请人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

发明人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

IPC分类号： H01L29/06 ,  H01L23/02

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S438/974 ,  H01L2924/00

摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

公开(公告)号：US07057259B2

公开(公告)日：2006-06-06

申请号：US10101337

申请日：2002-03-20

申请人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

发明人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

IPC分类号： H01L29/06

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S438/974 ,  H01L2924/00

摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

公开(公告)号：US20060076624A1

公开(公告)日：2006-04-13

申请号：US11282784

申请日：2005-11-18

申请人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/76251 ,  H01L21/84

摘要： A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.

摘要翻译： 公开了一种半导体衬底，其包括第一单晶硅层，形成为部分地覆盖第一单晶硅层的一个主表面的绝缘体，形成为覆盖第一单晶硅层的区域的第二单晶硅层， 不覆盖绝缘体，并且覆盖邻近该区域的绝缘体的边缘部分，以及形成在绝缘体上的非单晶硅层，非单晶硅层与第二单晶硅之间的界面 层位于绝缘体上。

公开(公告)号：US08532615B2

公开(公告)日：2013-09-10

申请号：US12395445

申请日：2009-02-27

申请人： Hajime Nagano

发明人： Hajime Nagano

IPC分类号： H04M1/66

CPC分类号： H04W60/04 ,  G08B25/008 ,  H04W84/045

摘要： To provide a security technique (a base station and a mobile terminal) for easily guarding a building such as a house for an average family or a small office at a low price by using a cellular phone terminal and a small base station (femtocell). A base station (FCL) of a mobile communication system placed in a building includes a communication unit (140) for communicating with the mobile communication system via a communication line; an obtaining unit (123) for obtaining an opened state of a fitting set to an opening of the building from the fitting or a switch placed near the fitting for detecting the opened state of the fitting; a registering unit (121) for registering information on a mobile terminal that uses the base station; a processing unit (122) for processing location registration of the mobile terminal; and a control unit (120) for controlling the communication unit to transmit a predetermined message to a predetermined addressee via the communication line if information received from the mobile terminal does not match the information registered in the registering unit when the location registration of the mobile terminal is performed by the processing unit after the opened state of the fitting is obtained.

摘要翻译： 为了提供一种安全技术（基站和移动终端），通过使用蜂窝电话终端和小型基站（femtocell），以便于以较低的价格容易地保护一般家庭或小型办公室的建筑物。 放置在建筑物中的移动通信系统的基站（FCL）包括通信单元（140），用于经由通信线路与移动通信系统进行通信; 获取单元（123），用于从配件或设置在配件附近的开关中获得对建筑物的开口设置的配件的打开状态，以检测配件的打开状态; 注册单元，用于在使用该基站的移动终端上注册信息; 处理单元（122），用于处理移动终端的位置登记; 以及控制单元（120），用于当移动终端的位置登记时，控制通信单元经由通信线路将预定消息发送到预定的收件人，如果从移动终端接收到的信息与注册单元中登记的信息不匹配 在获得配件的打开状态之后由处理单元执行。

公开(公告)号：US07884415B2

公开(公告)日：2011-02-08

申请号：US12405457

申请日：2009-03-17

申请人： Hajime Nagano

发明人： Hajime Nagano

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： In a semiconductor device, each of a plurality of floating gate electrodes has an upper end, a lower end and an intermediate portion between the upper and lower ends and is formed so that the intermediate portion has a smaller length in a gate-length direction than each of the upper and lower ends. Each of a plurality of control gate electrodes has an upper end, a lower end and an intermediate portion between the upper and lower ends and is formed so that the intermediate portion has a smaller length in a gate-length direction than each of the upper and lower ends. Each of a plurality of inter-electrode insulating films includes a first air gap formed in a first portion corresponding to the intermediate portion of each floating gate electrode and a second air gap formed in a second portion corresponding to the intermediate portion of each control gate electrode.

摘要翻译： 在半导体器件中，多个浮栅电极中的每一个具有上端和下端以及位于上端和下端之间的中间部分，并且形成为使得中间部分的栅极长度方向上的长度小于 每个上下端。 多个控制栅电极中的每一个具有上端，下端和位于上端和下端之间的中间部分，并且形成为使得中间部分在栅极长度方向上的长度小于上部和下部中的每一个 下端 多个电极间绝缘膜中的每一个包括形成在与每个浮栅电极的中间部分对应的第一部分中的第一气隙和形成在与每个控制栅电极的中间部分对应的第二部分中的第二气隙 。

公开(公告)号：US07598562B2

公开(公告)日：2009-10-06

申请号：US11769423

申请日：2007-06-27

申请人： Hajime Nagano ,  Takeo Furuhata

发明人： Hajime Nagano ,  Takeo Furuhata

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined on the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.

摘要翻译： 一种半导体器件，包括半导体衬底; 元件隔离区域，其具有填充有限定在所述半导体衬底上的绝缘膜的沟槽; 形成在由所述半导体衬底的元件隔离区隔离的元件形成区域中的存储单元晶体管; 并且所述存储单元晶体管包括形成在所述元件形成区域的表面上的栅极绝缘膜; 形成在栅绝缘膜上的浮栅; 一体地形成栅绝缘膜，以覆盖浮动栅极和元件隔离区域的绝缘膜，并且在对应于浮栅的部分和低介电常数的部分中具有高介电常数，在与绝缘膜相对应的部分 元件隔离区; 以及通过栅极间绝缘膜堆叠在浮置栅极上的控制栅极。

公开(公告)号：US07525154B2

公开(公告)日：2009-04-28

申请号：US10852511

申请日：2004-05-25

申请人： Hajime Nagano ,  Ichiro Mizushima ,  Kiyotaka Miyano

发明人： Hajime Nagano ,  Ichiro Mizushima ,  Kiyotaka Miyano

IPC分类号： H01L29/72

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78687

摘要： A semiconductor substrate and a manufacturing method therefore, and a semiconductor device using the semiconductor substrate comprise a strained Si region and unstrained Si region formed at substantially the same level. In an aspect of the invention, a semiconductor substrate is provided by comprising a support substrate, a first semiconductor region including a first silicon layer formed above the support substrate, a second semiconductor region including a strained second silicon layer formed above the support substrate, a surface of the second silicon layer being formed at substantially the same level as a surface of the first silicon layer, and an insulating film at an interface between the first semiconductor region and the second semiconductor region.

摘要翻译： 因此，半导体衬底及其制造方法以及使用该半导体衬底的半导体器件包括形成在大致相同电平的应变Si区域和未应变Si区域。 在本发明的一个方面中，提供一种半导体衬底，其包括支撑衬底，包括形成在支撑衬底上方的第一硅层的第一半导体区域，包括形成在支撑衬底上方的应变第二硅层的第二半导体区域， 所述第二硅层的表面形成在与所述第一硅层的表面基本相同的水平面上，以及在所述第一半导体区域和所述第二半导体区域之间的界面处形成绝缘膜。