公开(公告)号：US08207032B2

公开(公告)日：2012-06-26

申请号：US12872705

申请日：2010-08-31

申请人： Mark Fischer ,  Sanh D. Tang

发明人： Mark Fischer ,  Sanh D. Tang

IPC分类号： H01L21/8242 ,  H01L21/8238

CPC分类号： H01L27/10876 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/2454 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

摘要： Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

摘要翻译： 一些实施例包括形成垂直晶体管的方法。 结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。 每个鳍片可以具有垂直的晶体管柱，并且每个垂直晶体管柱可以具有底部源极/漏极区域位置，在底部源极/漏极区域位置上方的沟道区域位置，以及顶部源极/漏极区域 渠道区域位置。 导电栅极材料可以沿着鳍片形成，同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。 氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。 在一些实施例中，可以在形成导电栅极材料之后去除氧化物。

公开(公告)号：US20110276535A1

公开(公告)日：2011-11-10

申请号：US12895833

申请日：2010-09-30

申请人： Olivier Pin ,  Etienne Giraudy ,  Orjan Kjellberg ,  Mark Fischer ,  Steven Tamm ,  Varadarajan Rajaram

发明人： Olivier Pin ,  Etienne Giraudy ,  Orjan Kjellberg ,  Mark Fischer ,  Steven Tamm ,  Varadarajan Rajaram

IPC分类号： G06F17/00

CPC分类号： G06Q10/10

摘要： A computer implemented method a document management workflow in a multi-tenant system environment is disclosed. The method includes receiving instructions to create a composition a document. The document is encapsulated in a knowledge article version and the knowledge article version having a document category. The knowledge article version is associated with a knowledge article. The method further includes invoking the document management workflow that is specific to the knowledge article, the knowledge article version and the document category and configuring the document management workflow to include a plurality of workflow steps based on the knowledge article, the knowledge article version and the document category. Each of the plurality of workflow steps are then associated with one or more triggers and actor roles. The actor roles define permissible actions in each of the plurality of workflow steps. Data in the knowledge article and the knowledge article version are configured to be updated with the movement of a document in the plurality of workflow steps. The document management workflow provides cyclic processing steps with no termination state.

摘要翻译： 公开了一种在多租户系统环境中的文档管理工作流程的计算机实现方法。 该方法包括接收用于创建文档的组合的指令。 该文档封装在知识文章版本中，知识文章版本具有文档类别。 知识文章版本与知识文章相关联。 该方法还包括调用特定于知识文章，知识文章版本和文档类别的文档管理工作流，并且将文档管理工作流配置为包括基于知识文章，知识文章版本和 文件类别。 然后，多个工作流步骤中的每一个与一个或多个触发器和演员角色相关联。 演员角色定义了多个工作流程步骤中的每一个中的允许动作。 知识文章和知识文章版本中的数据被配置为随着多个工作流步骤中文档的移动而被更新。 文档管理工作流提供无终止状态的循环处理步骤。

公开(公告)号：US20070148853A1

公开(公告)日：2007-06-28

申请号：US11711548

申请日：2007-02-26

申请人： John Moore ,  Mark Fischer

发明人： John Moore ,  Mark Fischer

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28202 ,  H01L21/3115 ,  H01L21/3144 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/78

摘要： A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.

摘要翻译： 一种用于制造改进的集成电路器件的方法。 该方法能够选择性地硬化栅极氧化物层，并且包括提供其上形成有栅极氧化物层的半导体衬底。 然后在栅极氧化物层上形成抗蚀剂，并将其图案化以暴露待硬化的栅极氧化物层的一个或多个区域。 然后使用真正的远程等离子体氮化（RPN）方案或高密度等离子体（HDP）RPN方案使栅极氧化物层的暴露部分硬化。 由于本发明方法中使用的RPN方案在低温下运行，图案化的抗蚀剂通过RPN工艺保持稳定，并且由图案化的抗蚀剂暴露的那些栅极氧化物层的那些区域通过RPN处理选择性硬化，而 由图案化的抗蚀剂覆盖的区域保持不受影响。

公开(公告)号：US06900138B1

公开(公告)日：2005-05-31

申请号：US09259762

申请日：1999-03-01

申请人： Zhiping Yin ,  Mark Fischer

发明人： Zhiping Yin ,  Mark Fischer

IPC分类号： H01L21/027 ,  H01L21/318 ,  H01L21/302

CPC分类号： H01L21/3185 ,  H01L21/0274

摘要： The present invention includes a method for preventing distortion in semiconductor fabrication. The method comprises providing a substrate comprising a film comprising silicon nitride. The substrate is treated in a vacuum of about 3.0-6.5 Torr in an atmosphere comprising oxygen plasma wherein the oxygen plasma flow rate is at least about 300 sccm oxygen. A resist is applied to the treated substrate and the resist is patterned over the treated substrate.

摘要翻译： 本发明包括一种用于防止半导体制造中的变形的方法。 该方法包括提供包含含氮化硅的膜的衬底。 在包含氧等离子体的气氛中，在约3.0-6.5乇的真空中处理衬底，其中氧等离子体流速为至少约300sccm的氧气。 将抗蚀剂施加到经处理的基底上，并且将抗蚀剂图案化在经处理的基底上。

公开(公告)号：US06677661B1

公开(公告)日：2004-01-13

申请号：US09429220

申请日：1999-10-28

申请人： Scott Jeffrey DeBoer ,  John T. Moore ,  Mark Fischer ,  Randhir P. S. Thakur

发明人： Scott Jeffrey DeBoer ,  John T. Moore ,  Mark Fischer ,  Randhir P. S. Thakur

IPC分类号： H01L2358

CPC分类号： H01L21/28123 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/3185

摘要： In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer. In yet another aspect, the invention includes semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) a layer of silicon nitride over the substrate, the layer comprising a thickness and two portions elevationally displaced relative to one another, a first of the two portions having less resistance than a second of the two portions, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.

摘要翻译： 一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）用硅富集氮化硅层的一部分厚度，该部分包含小于或等于氮化硅层厚度的约95％。 在另一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）相对于所述氮化硅层的第二部分的折射率增加所述氮化硅层的厚度的第一部分的折射率，所述第一部分包括小于或等于所述氮化硅层的厚度的约95％ 氮化硅层。 在另一方面，本发明包括半导体晶片组件，包括：a）半导体晶片衬底; 以及b）在所述衬底上的一层氮化硅，所述层包括相对于彼此高度位移的厚度和两个部分，所述两个部分中的第一部分具有比所述两个部分中的第二部分更小的电阻，所述第一部分包括小于 或等于氮化硅层厚度的约95％。

公开(公告)号：US06670288B1

公开(公告)日：2003-12-30

申请号：US09604850

申请日：2000-06-27

申请人： Scott Jeffrey DeBoer ,  John T. Moore ,  Mark Fischer ,  Randhir P. S. Thakur

发明人： Scott Jeffrey DeBoer ,  John T. Moore ,  Mark Fischer ,  Randhir P. S. Thakur

IPC分类号： H01L2131

CPC分类号： H01L21/28123 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/3185

摘要： In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer. In yet another aspect, the invention includes semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) a layer of silicon nitride over the substrate, the layer comprising a thickness and two portions elevationally displaced relative to one another, a first of the two portions having less resistance than a second of the two portions, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.

摘要翻译： 一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）用硅富集氮化硅层的一部分厚度，该部分包含小于或等于氮化硅层厚度的约95％。 在另一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）相对于所述氮化硅层的第二部分的折射率增加所述氮化硅层的厚度的第一部分的折射率，所述第一部分包括小于或等于所述氮化硅层的厚度的约95％ 氮化硅层。 在另一方面，本发明包括半导体晶片组件，包括：a）半导体晶片衬底; 以及b）在所述衬底上的一层氮化硅，所述层包括相对于彼此高度位移的厚度和两个部分，所述两个部分中的第一部分具有比所述两个部分中的第二部分更小的电阻，所述第一部分包括小于 或等于氮化硅层厚度的约95％。

公开(公告)号：US06440850B1

公开(公告)日：2002-08-27

申请号：US09385586

申请日：1999-08-27

申请人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

发明人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

IPC分类号： H01L2144

CPC分类号： H01L23/485 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.

摘要翻译： 在DRAM芯片的结构内提供导电板触点的网络，以便能够在每个电荷存储区域中存储非零电压电平。 改进的电池或顶板接触提供低接触电阻和改进的结构完整性，使得接触在随后的加工步骤期间更不易于去除。 顶板共形地将图案化的容器图案化成一个子区域。 金属接触结构包括腰部，接触腿和锚腿。 接触腿与容器内部的顶板接触。 腰部将接触腿的顶部连接到锚腿的顶部并且在顶板的边缘上延伸。 锚腿向下延伸穿过与容器相邻但与容器间隔开的子区域，以将结构锚定在适当位置并提供结构完整性。 因此，本发明提供了一种与导电薄膜接触的改进的结构，具有低的接触电阻和改进的结构完整性。

公开(公告)号：US06376358B1

公开(公告)日：2002-04-23

申请号：US09809666

申请日：2001-03-15

申请人： Mark Fischer ,  Jigish D. Trivedi ,  Charles H. Dennison ,  Todd R. Abbott ,  Raymond A. Turi

发明人： Mark Fischer ,  Jigish D. Trivedi ,  Charles H. Dennison ,  Todd R. Abbott ,  Raymond A. Turi

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  G11C2207/104 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.

公开(公告)号：US06300253B1

公开(公告)日：2001-10-09

申请号：US09057155

申请日：1998-04-07

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L2131

CPC分类号： H01L21/31144 ,  G03F7/091 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/312

摘要： In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.

摘要翻译： 一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上形成光致抗蚀剂。 另一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; c）在阻挡层上形成光致抗蚀剂; d）将所述光致抗蚀剂暴露于图案化的光束以使所述光致抗蚀剂的至少一部分在溶剂中比其它部分更易溶，所述阻挡层是吸收通过所述光致抗蚀剂的光的抗反射表面; 以及e）将所述光致抗蚀剂暴露于所述溶剂以除去所述至少一个部分，同时将所述另一部分留在所述阻挡层上。 在另一方面，本发明包括半导体晶片组件，包括：a）氮化硅材料，该材料具有表面; b）在所述材料的表面上的阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上并抵靠所述阻挡层的光致抗蚀剂。

公开(公告)号：US6083803A

公开(公告)日：2000-07-04

申请号：US32254

申请日：1998-02-27

申请人： Mark Fischer ,  John K. Zahurak ,  Thomas M. Graettinger ,  Kunal Parekh

发明人： Mark Fischer ,  John K. Zahurak ,  Thomas M. Graettinger ,  Kunal Parekh

IPC分类号： H01L21/302 ,  G03F7/075 ,  G03F7/16 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10888 ,  G03F7/0757 ,  G03F7/167 ,  H01L21/76838 ,  H01L27/10852

摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.