公开(公告)号：US08595919B2

公开(公告)日：2013-12-03

申请号：US13095973

申请日：2011-04-28

Applicant: S. Jay Chey ,  Timothy C. Krywanczyk ,  Mohammed S. Shaikh ,  Matthew T. Tiersch ,  Cornelia Kang-I Tsang

Inventor： S. Jay Chey ,  Timothy C. Krywanczyk ,  Mohammed S. Shaikh ,  Matthew T. Tiersch ,  Cornelia Kang-I Tsang

IPC: B23P19/00

CPC classification number: G01R3/00 ,  G01R1/07378

Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.

Abstract translation: 提供了一种用于晶片的晶片级测试探针中的硅芯座，包括主体，第一和第二相对面以及通过主体形成的通孔阵列，以在第一和第二面之间延伸通过 分别与第一和第二表面上的每个通孔相关联的引线对可彼此电连接。

公开(公告)号：US20110199109A1

公开(公告)日：2011-08-18

申请号：US13095973

申请日：2011-04-28

Applicant: S. Jay Chey ,  Timothy C. Krywanczyk ,  Mohammed S. Shaikh ,  Matthew T. Tiersch ,  Cornelia Tsang

Inventor： S. Jay Chey ,  Timothy C. Krywanczyk ,  Mohammed S. Shaikh ,  Matthew T. Tiersch ,  Cornelia Tsang

IPC: G01R31/02 ,  G01R1/067

CPC classification number: G01R3/00 ,  G01R1/07378

Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.

Abstract translation: 提供了一种用于晶片的晶片级测试探针中的硅芯座，包括主体，第一和第二相对面以及通过主体形成的通孔阵列，以在第一和第二面之间延伸通过 分别与第一和第二表面上的每个通孔相关联的引线对可彼此电连接。

公开(公告)号：US07387911B2

公开(公告)日：2008-06-17

申请号：US10990778

申请日：2004-11-16

Applicant: David M Audette ,  Steven R. Codding ,  Timothy C. Krywanczyk ,  Brian J. Thibault ,  Matthew R. Whalen

Inventor： David M Audette ,  Steven R. Codding ,  Timothy C. Krywanczyk ,  Brian J. Thibault ,  Matthew R. Whalen

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/46 ,  H01L23/544 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/36 ,  H01L23/3737 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thermally conductive protective film or layer is applied to the backside surface of a semiconductor wafer prior to a subsequent dicing operation performed on the wafer to singulate the wafer into diced semiconductor chips, during which the thin thermally conductive film minimizes and prevents chipping and cracking damage to the wafer and diced chips. During subsequent electrical operation of a diced chip, the thin thermally conductive film functions as a thermal conductor to dissipate and conduct away to a heat sink any heat generated during operation of the chip.

Abstract translation: 在对晶片进行随后的切割操作之前，将导热保护膜或层施加到半导体晶片的背面，以便将晶​​片分成切割的半导体芯片，在此期间，薄导热膜最小化并防止切屑和破裂损伤 到晶圆和切片芯片。 在切割芯片的随后的电操作期间，薄的导热膜用作热导体，以在芯片的操作期间产生的热量消散并导向散热器。

公开(公告)号：US20080113458A1

公开(公告)日：2008-05-15

申请号：US11559990

申请日：2006-11-15

Applicant: Timothy C. Krywanczyk ,  Timothy E. Neary ,  Erik M. Probstfield

Inventor： Timothy C. Krywanczyk ,  Timothy E. Neary ,  Erik M. Probstfield

IPC: H01L21/66 ,  G06F17/50

CPC classification number: H01L22/20

Abstract: A method for inspecting a semiconductor wafer fabricated for image sensing operation that has had a transparent protective tape layer applied to a front or active wafer surface. The method includes quantifying chip defects in the image sensor wafer that lie under the protective layer using automatic disposition equipment.

Abstract translation: 一种用于检查制造用于图像感测操作的半导体晶片的方法，其具有施加到前面或活动晶片表面的透明保护带层。 该方法包括使用自动配置设备量化位于保护层下方的图像传感器晶片中的芯片缺陷。

公开(公告)号：US07025891B2

公开(公告)日：2006-04-11

申请号：US10604991

申请日：2003-08-29

Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Joseph D. Danaher ,  John C. Malinowski ,  James R. Palmer ,  Melvin T. Kelly ,  Caitlin W. Weinstein ,  Wolfgang Sauter

Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Joseph D. Danaher ,  John C. Malinowski ,  James R. Palmer ,  Melvin T. Kelly ,  Caitlin W. Weinstein ,  Wolfgang Sauter

IPC: B44C1/22 ,  C25F3/00

CPC classification number: H01L21/3212 ,  C23F3/06

Abstract: A method of treating a molybdenum (moly) mask used in a C4 process to pattern C4 contacts. The moly mask has a wafer side which contacts a wafer during the C4 process and has a rough surface that includes spikes/projections of moly. The moly mask also has a non wafer side and a plurality of holes extending through the mask to pattern C4 contacts in the C4 process. An adhesive layer, such as an adhesive tape, is applied to the non wafer side of the moly mask, to enable a polishing tool to pull a vacuum on the non wafer side of the moly mask in spite of the presence of the holes to secure the moly mask during a subsequent polishing step. The tape also functions as a cushion so that defects on the non wafer side of the moly mask do not replicate through the moly mask to the polished wafer side of the moly mask. The wafer side of the moly mask is then subjected to mechanical or chemical/mechanical polishing to substantially remove the spikes of moly without significantly altering the dimensions of the moly mask or the holes.

Abstract translation: 一种处理C4工艺中使用的钼（钼）掩模的图案化C4接触的方法。 钼掩模具有在C4工艺期间接触晶片的晶片侧，并且具有包括钼的尖峰/突起的粗糙表面。 钼掩模还具​​有非晶片侧和在C4工艺中延伸穿过掩模以形成图案C4触点的多个孔。 粘合剂层例如胶带被施加到钼掩模的非晶片侧，以使抛光工具能够在钼掩模的非晶片侧上拉真空，尽管存在孔以确保 在随后的抛光步骤期间的钼掩模。 胶带还起垫片的作用，使得钼掩模的非晶片侧的缺陷不会通过钼掩模复制到钼掩模的抛光晶片侧。 然后对钼掩模的晶片侧进行机械或化学/机械抛光，以基本上除去钼的尖峰而不显着改变钼掩模或孔的尺寸。

公开(公告)号：US06888223B2

公开(公告)日：2005-05-03

申请号：US10405763

申请日：2003-04-01

Applicant: Donald W. Brouillette ,  Joseph D. Danaher ,  Timothy C. Krywanczyk ,  Amye L. Wells

Inventor： Donald W. Brouillette ,  Joseph D. Danaher ,  Timothy C. Krywanczyk ,  Amye L. Wells

IPC: H01L21/768 ,  H01L23/048

CPC classification number: H01L21/76898

Abstract: A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e.g., photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.

Abstract translation: 一种结构和形成方法。 衬底在衬底的相对侧上具有前表面和后表面。 衬底具有从前表面测量的从后表面延伸到衬底的第二深度的背侧部分。 在衬底中形成至少一个通孔，并从前表面延伸到通孔深度进入衬底。 通孔深度特定于每个通孔。 每个通孔的通孔深度小于衬底的初始厚度。 第二深度不超过通孔深度的最小值。 将有机材料（例如光致抗蚀剂）插入每个通孔中。 随后用带覆盖有机材料，随后除去基材的背面部分。 随后从有机材料中取出胶带，然后从每个通孔中除去有机材料。