公开(公告)号：US20170069510A1

公开(公告)日：2017-03-09

申请号：US15247138

申请日：2016-08-25

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Angelique D. Raley ,  Nihar Mohanty ,  Aelan Mosden

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a second conformal spacer deposition using an oxide, the deposition creating a second conformal layer; performing a second spacer RIE process and a second pull process, wherein generating a second spacer pattern, the second spacer RIE process includes adsorption of N containing gas on a surface of the substrate which activates the surface to react with an F and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

Abstract translation: 提供了一种使用积分方案提高基板上的结构的图案密度的方法，所述方法包括：提供具有第一间隔图案和下层的基板，所述基底层包括第一下层，第二下层， 和目标层; 使用氧化物执行第二共形间隔物沉积，所述沉积产生第二共形层; 执行第二间隔RIE过程和第二拉伸工艺，其中产生第二间隔物图案，第二间隔物RIE方法包括将N含气体吸附在基底表面上，该表面激活表面以与F和/或H反应 的气体形成氟硅酸盐; 并且其中所述集成目标包括在目标间隔物蚀刻速率内选择性地蚀刻间隔膜，增强对第一下层和第二下层的同时选择性并防止图案损伤。

公开(公告)号：US12272558B2

公开(公告)日：2025-04-08

申请号：US17964601

申请日：2022-10-12

Applicant: TOKYO ELECTRON LIMITED

Inventor： Matthew Flaugh ,  Jonathan Hollin ,  Subhadeep Kal ,  Pingshan Luan ,  Hamed Hajibabaeinajafabadi ,  Yu-Hao Tsai ,  Aelan Mosden

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: Selective protection and etching is provided which can be utilized in etching of a silicon containing layer with respect to a Ge or SiGe layer. In an example, the layers are stacked, and an oxide is on a side surface of the layers. A treatment is utilized to provide a modified surface or termination surface on side surfaces of the Ge/SiGe layers, and a heat treatment is provided after the gas treatment to selectively sublimate layer portions on side surfaces of the Si containing layers. The gas treatment and heat treatment are preferably in non-plasma environments. Thereafter, a plasma process is performed to form a protective layer on the Ge containing layers, and the Si containing layers can be etched with the plasma.

公开(公告)号：US20240379372A1

公开(公告)日：2024-11-14

申请号：US18619628

申请日：2024-03-28

Applicant: Tokyo Electron Limited

Inventor： Adam Pranda ,  Christopher Catano ,  Yusuke Lent-Yoshida ,  Aelan Mosden ,  Yun Han ,  Ken Kobayashi

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a semiconductor device can include providing a substrate having a patterned structure comprising semiconductor materials, where the patterned structure has a side profile including indentations, such as a patterned film stack, and where a spacer layer is conformally deposited over the patterned structure and within the indentations, reacting a surface of the spacer layer with a plasma-excited first etch gas to form a reacted layer on the spacer layer, wherein the plasma-excited first etch gas includes fluorine, hydrogen, and nitrogen, and removing at least part of the reacted layer by ion bombardment from exposure to a plasma-excited second etch gas. The spacer layer can be SiOCN. The reacted layer can be ammonium fluorosilicate. The first etch gas can contain SF6, H2, and N2, or NF3, H2, and N2. The reacting and removing can be done at room temperature in a same chamber.

公开(公告)号：US20230420267A1

公开(公告)日：2023-12-28

申请号：US17826236

申请日：2022-05-27

Applicant: Tokyo Electron Limited

Inventor： Stephanie Oyola-Reynoso ,  Ivo Otto, IV ,  Qi Wang ,  Aelan Mosden

IPC: H01L21/3213

CPC classification number: H01L21/32138 ,  H01L21/76885 ,  H01L21/32139

Abstract: A method of processing a substrate that includes: forming an etch mask over a ruthenium (Ru) metal layer of a substrate, the etch mask exposing a first portion of the Ru metal layer and covering a second portion of the Ru metal layer; and converting the first portion of the Ru metal layer into a volatile Ru etch product in a processing chamber, the converting including exposing the Ru metal layer of the substrate to a halogen-containing vapor, and to a ligand-exchange agent to form the volatile Ru etch product, where the converting is an oxygen-free process.

公开(公告)号：US20220351970A1

公开(公告)日：2022-11-03

申请号：US17862820

申请日：2022-07-12

Applicant: Tokyo Electron Limited

Inventor： Pingshan Luan ,  Christopher Catano ,  Aelan Mosden

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/311 ,  H01J37/32

Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.

公开(公告)号：US11424120B2

公开(公告)日：2022-08-23

申请号：US17155772

申请日：2021-01-22

Applicant: Tokyo Electron Limited

Inventor： Pingshan Luan ,  Christopher Catano ,  Aelan Mosden

IPC: H01L21/02 ,  H01J37/32 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3213

Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.

公开(公告)号：US20220238344A1

公开(公告)日：2022-07-28

申请号：US17161199

申请日：2021-01-28

Applicant: Tokyo Electron Limited

Inventor： Pingshan Luan ,  Aelan Mosden

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01J37/32

Abstract: In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a film stack. The film stack includes first and second germanium-containing layers and a first silicon layer positioned between the first and second germanium-containing layers. The method includes selectively etching the first silicon layer by exposing the film stack to a plasma that includes fluorine agents and nitrogen agents. The plasma etches the first silicon layer, and causes a passivation layer to be formed on exposed surfaces of the first and second germanium-containing layers to inhibit etching of the first and second germanium-containing layers during exposure of the film stack to the plasma.

公开(公告)号：US10971372B2

公开(公告)日：2021-04-06

申请号：US15191956

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

公开(公告)号：US10600687B2

公开(公告)日：2020-03-24

申请号：US15491786

申请日：2017-04-19

Applicant: Tokyo Electron Limited

Inventor： Aelan Mosden ,  Kaushik Kumar

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L21/033 ,  H01L29/66

Abstract: Process integration techniques are disclosed that use a carbon fill layer during formation of self-aligned structures. A carbon layer may be placed over an etch stop layer. A cap layer may be provided over the carbon layer. The carbon layer may fill a high aspect ratio structure formed on the substrate. The carbon layer may be removed from a substrate in a highly selective removal technique in a manner that does not damage underlying layers. The carbon layer may fill a self-aligned contact region that is provided for a self-aligned contact process flow. A tone inversion mask may be used to protect multiple self-aligned contact regions. With the blocking mask in place, the carbon layer may be removed from regions that are not the self-aligned contact region. After removal of the blocking mask, the carbon layer which fills the self-aligned contacts may then be removed.

公开(公告)号：US10573564B2

公开(公告)日：2020-02-25

申请号：US15965606

申请日：2018-04-27

Applicant: Tokyo Electron Limited

Inventor： Aelan Mosden ,  Cheryl Pereira ,  Subhadeep Kal

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/786 ,  H01L29/08 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/423

Abstract: Embodiments of the invention provide a method for forming NFET, PFET, or NFET and PFET nanowire devices on a substrate. According to one embodiment, the method includes providing a film stack containing a Si layer, a SiGe layer, and a Ge layer positioned between the Si layer and the SiGe layer, and selectively removing the Ge layer by etching that is selective to the Si layer and the SiGe layer, thereby forming an opening between the Si layer and the SiGe layer. According to another embodiment, the method providing a film stack containing alternating Si and Ge layers, and selectively removing the Ge layers by etching that is selective to the Si layers. According to another embodiment, the method includes providing a film stack containing a plurality of alternating SiGe and Ge layers, and selectively removing the plurality of Ge layers by etching that is selective to the SiGe layers.