公开(公告)号：US08405432B2

公开(公告)日：2013-03-26

申请号：US12963114

申请日：2010-12-08

申请人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

发明人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

IPC分类号： H03K3/01

CPC分类号： H03K19/00384 ,  H03K19/01721

摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.

摘要翻译： 根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置 以使得能够选择性地驱动多个缓冲电路。 多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据 控制信号由外部提供。 包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

公开(公告)号：US08072830B2

公开(公告)日：2011-12-06

申请号：US12437123

申请日：2009-05-07

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： G11C29/08

CPC分类号： G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C2207/104 ,  G11C2207/105

摘要： A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

摘要翻译： 半导体集成电路器件包括多个存储器宏，宏公共寄存器块和存储器宏操作设置电路。 宏公共寄存器块具有宏公共寄存器，其设置在多个存储器宏之外，并且向多个存储器宏提供存储器宏操作指定信号。 存储器宏操作设置电路分别设置在多个存储器宏中，并且分别被配置为响应于从宏公共寄存器提供的存储器宏操作指定信号来设置存储器宏的操作状态。

公开(公告)号：US20110148211A1

公开(公告)日：2011-06-23

申请号：US12885935

申请日：2010-09-20

申请人： Fumiyoshi MATSUOKA ,  Ryo Fukuda

发明人： Fumiyoshi MATSUOKA ,  Ryo Fukuda

IPC分类号： H02J4/00

CPC分类号： H02M3/157 ,  Y10T307/696

摘要： In a semiconductor device according to the embodiment, a core circuit is an IC. A peripheral circuit includes a driver supplied with voltages from an internal power source and an external power source and outputting data transferred from the core circuit, and a fetch portion transferring the digital data to the driver. A first power source supplies an internal voltage to the driver via a power source line. A second power source includes current driving strings each including a current driving element and a switching element connected in series between the external power source and the power source line. The second power source supplies a current to the power source line separately from the first power source line by driving the current driving strings. A power source controller controls the second power source to drive the current driving strings when a logic transition occurs among consecutive bits of the data.

摘要翻译： 在根据实施例的半导体器件中，核心电路是IC。 外围电路包括从内部电源和外部电源提供电压的驱动器，并输出从核心电路传送的数据，以及将数字数据传送给驱动器的取出部分。 第一电源通过电源线向驱动器提供内部电压。 第二电源包括各自包括串联连接在外部电源和电源线之间的电流驱动元件和开关元件的电流驱动串。 第二电源通过驱动当前驱动串来将电流与第一电源线分开地提供给电源线。 当在数据的连续位之间发生逻辑转换时，电源控制器控制第二电源来驱动当前驱动串。

公开(公告)号：US20110128063A1

公开(公告)日：2011-06-02

申请号：US12884533

申请日：2010-09-17

申请人： Ryo Fukuda ,  Masaru Koyanagi

发明人： Ryo Fukuda ,  Masaru Koyanagi

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二电平移位电路。 第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。 第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号 移位器被输入。 第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

公开(公告)号：US07888769B2

公开(公告)日：2011-02-15

申请号：US11756196

申请日：2007-05-31

申请人： Masaki Kondo ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

发明人： Masaki Kondo ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

IPC分类号： H01L29/00

CPC分类号： H01L27/0251 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.

摘要翻译： 根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

公开(公告)号：US07859897B2

公开(公告)日：2010-12-28

申请号：US12402030

申请日：2009-03-11

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： G11C7/00

CPC分类号： G11C8/10 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and drain layer and lower than the other of the potentials of the source and drain layer so that electric charges flow in the body region, and a potential of the second gate electrode is set to be higher as an absolute value than those of potentials of the source layer, drain layer, and first gate electrode so that electric charges flow from the body region, and in the data holding state, the memory cell is kept in a stationary state that a first amount of the electric charges flowing in the body region per unit time is substantially the same as a second amount of the electric charges flowing from the body region per unit time.

摘要翻译： 存储器包括：包括浮体的存储单元，其中在数据保持状态下，第一栅电极的电位被设置为高于源极和漏极层的电位之一并且低于源极的另一个电位 漏极层，使得电荷在体区域流动，并且将第二栅电极的电位设定为比源极层，漏极层和第一栅电极的电位的绝对值高，使得电荷 从身体区域流出，并且在数据保持状态下，存储单元保持在静止状态，即在单位时间内在体区域中流动的电荷的第一量与第二电荷量基本相同 每单位时间从身体区域流出。

公开(公告)号：US07697318B2

公开(公告)日：2010-04-13

申请号：US11964260

申请日：2007-12-26

申请人： Ryo Fukuda ,  Daisaburo Takashima

发明人： Ryo Fukuda ,  Daisaburo Takashima

IPC分类号： G11C11/24

CPC分类号： G11C11/405 ,  G11C5/063 ,  G11C7/18 ,  G11C8/14 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10897

摘要： A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.

摘要翻译： 存储单元阵列包括布置在位线对和字线的交点处的多个存储单元。 每个存储单元包括具有连接到第一位线的一个主电极的第一晶体管，具有连接到第二位线的一个主电极的第二晶体管，用于数据存储的第一节点电极连接到第一晶体管的另一个主电极 ，连接到第二晶体管的另一个主电极的用于数据存储的第二节点电极和围绕第一和第二节点电极形成的屏蔽电极。 第一和第二晶体管具有连接到相同字线的相应门，并且第一和第二位线连接到相同的感测放大器。 第一和第二节点电极，第一和第二位线，字线和屏蔽电极使用绝缘膜彼此隔离。

公开(公告)号：US07406637B2

公开(公告)日：2008-07-29

申请号：US11008270

申请日：2004-12-10

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/36 ,  G11C2029/3602

摘要： A semiconductor memory device comprises a memory core, data control circuit, flag register, data register and computation circuit. The memory core has a plurality of memory cells for storing data. The data control circuit writes and reads first test data to and from the memory cells in synchrony with a clock signal. The flag register stores a plurality of flag data items. The data register stores second test data input corresponding to input of a command. The computation circuit performs, at every cycle, computation of the second test data, stored in the data register, and each of the flag data items stored in the flag register, thereby generating the first test data, until an n-th (n is a positive integer) cycle of the clock signal is reached. The first test data is written to the memory cells by the data control circuit.

摘要翻译： 半导体存储器件包括存储器核，数据控制电路，标志寄存器，数据寄存器和计算电路。 存储器核具有用于存储数据的多个存储单元。 数据控制电路与时钟信号同步地向存储器单元写入和读出第一测试数据。 标志寄存器存储多个标志数据项。 数据寄存器存储对应于命令输入的第二测试数据输入。 计算电路在每个周期执行存储在数据寄存器中的第二测试数据和存储在标志寄存器中的每个标志数据项的计算，从而生成第一测试数据，直到第n（n是 时钟信号的正整数）周期。 第一测试数据由数据控制电路写入存储单元。

公开(公告)号：US20060119415A1

公开(公告)日：2006-06-08

申请号：US11293378

申请日：2005-12-05

申请人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

发明人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

IPC分类号： H01H37/76

CPC分类号： H01L23/5258 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.

摘要翻译： 一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为 并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

公开(公告)号：US06865126B2

公开(公告)日：2005-03-08

申请号：US10933517

申请日：2004-09-03

申请人： Ryo Fukuda

发明人： Ryo Fukuda

IPC分类号： G11C29/04 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C29/00 ,  G11C7/00 ,  G06F12/00 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C29/848 ,  G11C11/4096 ,  G11C2207/002

摘要： A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

摘要翻译： 半导体存储器件包括数据线移位电路，分别连接到多个读出放大器写入电路的多个数据屏蔽线以及多个掩模电路。 多个屏蔽电路各自包括至少一个移位开关电路，并将掩模信号提供给读出放大器写入电路，读出放大器写入电路连接到不同于数据线被数据线移位电路移位之前的掩模电路，通过 移位开关电路，并将掩模信号提供给读出放大器写入电路，该读取电路写入电路连接到与数据线移位之前相同的屏蔽电路，而不是通过移位开关电路。