公开(公告)号：US06713826B2

公开(公告)日：2004-03-30

申请号：US10356501

申请日：2003-02-03

申请人： Takashi Uehara ,  Masato Kanazawa

发明人： Takashi Uehara ,  Masato Kanazawa

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656

摘要： A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.

摘要翻译： 栅电极由多晶硅的下电极和包括低电阻膜的上电极组成。 氮化物侧壁形成为至少覆盖绝缘体盖和上电极的侧面。 形成衬垫氧化膜以覆盖下电极的侧面的至少一部分和半导体衬底的上表面的一部分。 由于形成第二氮化物侧壁以覆盖第一氮化物侧壁和衬垫氧化物膜，因此可以通过蚀刻形成自对准接触孔。 结果，可以获得具有高度可靠的自对准接触的半导体器件。

公开(公告)号：US06573132B1

公开(公告)日：2003-06-03

申请号：US09515673

申请日：2000-02-29

申请人： Takashi Uehara ,  Masato Kanazawa

发明人： Takashi Uehara ,  Masato Kanazawa

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656

摘要： A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.

公开(公告)号：US6124160A

公开(公告)日：2000-09-26

申请号：US192536

申请日：1998-11-17

申请人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

发明人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

IPC分类号： H01L29/43 ,  H01L21/02 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8242

CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11543 ,  H01L28/40 ,  Y10S438/957

摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.

摘要翻译： MOS晶体管包括栅极氧化膜和通过第一和第二导体膜的叠层形成的栅电极。 电容元件包括由第一导体膜形成的下部电容电极，由与栅极氧化膜不同的绝缘膜制成的电容膜，由电容膜上的第二导体膜形成的上部电容电极，以及引线 电极由第二导电膜形成。 以与使用栅极氧化膜作为电容膜的情况相同的步骤，可以制造具有设置的电容膜的半导体器件，电容膜由与氮化物膜不同的氮化物膜等构成 栅氧化膜。 因此，使用具有每单位面积的大的电容值的电容膜，从而可以减小占用面积并且可以控制制造成本的增加。 在其中提供晶体管，电容元件，电阻膜等的半导体器件中，可以减小占用面积并且可以减少制造成本。

公开(公告)号：US6118738A

公开(公告)日：2000-09-12

申请号：US74666

申请日：1998-05-08

申请人： Takashi Uehara

发明人： Takashi Uehara

IPC分类号： G11B17/22 ,  G11B27/00 ,  G11B27/11 ,  G11B27/34 ,  G11B27/36

CPC分类号： G11B17/228 ,  G11B27/002 ,  G11B27/11 ,  G11B2220/2545 ,  G11B2220/2562 ,  G11B2220/65 ,  G11B27/34 ,  G11B27/36

摘要： The present invention provides a disk storage device capable of storing a plurality of types of disks, or a plurality of disks of the same type, and managing these disks easily to improve the operability of the apparatus. The invention reproduces the contents of the disks at high continuity even as disks of different types are exchanged. In order to manage disks stored in the disk storage device efficiently, there is provided the disk manager information memory device having the memory unit, in which the disk storage location data, disk type data and control data necessary for reproducing each disk are pre-stored together with additional data for managing each disk. When the additional data of a disk is input from an outside source, the management additional data which matches with the input additional data is searched, and the disk storage location data, data type data and control data, associated with the input additional data are read from the memory unit of the disk manager to be searched.

摘要翻译： 本发明提供一种能够存储多种类型的盘或相同类型的多个盘的盘存储装置，并且容易地管理这些盘以提高装置的可操作性。 即使交换了不同类型的盘，本发明也以高连续性再现盘的内容。 为了有效地管理存储在磁盘存储装置中的磁盘，提供了具有存储单元的磁盘管理器信息存储装置，其中盘存储位置数据，磁盘类型数据和再现每个磁盘所需的控制数据被预先存储 以及用于管理每个磁盘的附加数据。 当从外部源输入磁盘的附加数据时，搜索与输入的附加数据匹配的管理附加数据，并读取与输入的附加数据相关联的盘存储位置数据，数据类型数据和控制数据 从要被搜索的磁盘管理器的存储器单元。

公开(公告)号：US06108445A

公开(公告)日：2000-08-22

申请号：US891985

申请日：1997-07-14

申请人： Takashi Uehara

发明人： Takashi Uehara

IPC分类号： G06F15/02 ,  G06F3/00 ,  G06F3/01 ,  G06F3/033 ,  G06F3/041 ,  G06F3/048 ,  G06F17/22 ,  G06F17/28 ,  G06K9/00

CPC分类号： G06F3/018 ,  G06F17/2863 ,  G06F3/0488

摘要： An input device including a display unit for displaying thereon characters entered from a keyboard or by a pen inputting operation, a character selector including a tablet for selecting any character from among the characters displayed on the display unit, and a CPU for receiving the characters selected by the character selector as a new input. When any character is selected from an already input character string displayed on the display unit, the selected character is added as a new character input to the already input characters, and displayed together on the display unit.

摘要翻译： 一种输入装置，包括显示单元，用于显示从键盘输入的字符或通过笔输入操作;字符选择器，包括用于从显示在显示单元上的字符中选择任何字符的图形输入板，以及用于接收所选择的字符的CPU 由字符选择器作为新的输入。 当从显示单元上显示的已经输入的字符串中选择任何字符时，所选择的字符作为新的字符输入被添加到已经输入的字符，并且一起显示在显示单元上。

公开(公告)号：US5698902A

公开(公告)日：1997-12-16

申请号：US574368

申请日：1995-12-18

申请人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takashi Nakabayashi ,  Minoru Fujii

发明人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takashi Nakabayashi ,  Minoru Fujii

IPC分类号： H01L21/336 ,  H01L23/485 ,  H01L29/423 ,  H01L29/78 ,  H01L23/48

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L23/485 ,  H01L29/42376 ,  H01L29/7833 ,  H01L2924/0002 ,  Y10S438/926

摘要： There are provided: an isolation protruding upward from a semiconductor substrate in an active region; a gate electrode formed in the active region; and a pair of dummy electrodes formed to extend over the active region and the isolation and substantially in parallel with the gate electrode. Each of the gate electrode and dummy electrodes is composed of a lower film and an upper film. The lower films of the dummy electrodes are formed flush with the isolation and in contact with the side edges of the isolation. With the dummy electrodes, any gate electrode can be formed in a line-and-space pattern, so that the finished sizes of the gate electrode become uniform. This enables a reduction in gate length and therefore provides a semiconductor device of higher integration which is operable at a higher speed and substantially free from variations in finished size resulting from the use of different gate patterns.

摘要翻译： 提供：在有源区域中从半导体衬底向上突出的隔离件; 形成在有源区中的栅电极; 以及一对虚拟电极，其形成为在有源区域上延伸并且隔离并且基本上与栅电极平行。 栅电极和虚拟电极各自由下膜和上膜构成。 虚拟电极的下部薄膜与隔离件的侧边缘隔离形成平齐的表面。 利用虚拟电极，可以以线间距图案形成任何栅电极，使得栅电极的成品尺寸变得均匀。 这使得能够减小栅极长度并因此提供更高集成度的半导体器件，该半导体器件可以以更高的速度操作，并且基本上不受使用不同栅极图案造成的成品尺寸的变化。

公开(公告)号：US5618748A

公开(公告)日：1997-04-08

申请号：US443266

申请日：1995-05-17

申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

IPC分类号： H01L21/8238 ,  H01L21/70

CPC分类号： H01L21/823814 ,  Y10S148/147

摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

公开(公告)号：US5447872A

公开(公告)日：1995-09-05

申请号：US340375

申请日：1994-11-14

申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823814 ,  Y10S148/147

摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

公开(公告)号：US5030582A

公开(公告)日：1991-07-09

申请号：US418039

申请日：1989-10-06

申请人： Akio Miyajima ,  Keiichi Kagawa ,  Akihira Shinohara ,  Kiyoyuki Morita ,  Takashi Uehara

发明人： Akio Miyajima ,  Keiichi Kagawa ,  Akihira Shinohara ,  Kiyoyuki Morita ,  Takashi Uehara

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0928

摘要： An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from being exposed to ion implantation. The prevention of the exposure of the gate electrode to the ion implantation ensures the prevention of channeling in the gate electrode.

摘要翻译： 在基板上延伸的栅电极上形成离子注入阻挡层。 当将离子注入到衬底中以在衬底中形成LDD层或源极和漏极区域时，阻挡层用于防止栅电极暴露于离子注入。 防止栅电极暴露于离子注入确保防止栅电极中的沟道化。

公开(公告)号：US4885833A

公开(公告)日：1989-12-12

申请号：US253451

申请日：1988-10-05

申请人： Shigehiro Umegai ,  Teruhisa Noguchi ,  Hirobumi Morita ,  Takashi Uehara ,  Takayuki Hoshino

发明人： Shigehiro Umegai ,  Teruhisa Noguchi ,  Hirobumi Morita ,  Takashi Uehara ,  Takayuki Hoshino

IPC分类号： B62D65/06

CPC分类号： B62D65/06 ,  Y10T29/49769 ,  Y10T29/49771 ,  Y10T29/53004 ,  Y10T29/53013 ,  Y10T29/53039

摘要： A robot having a robot arm swingable from a position outside a car body conveying line to the line and movable in the directions of length, width and height of the car body is provided with a support frame carrying a jig for holding the window glass. The frame is tiltably mounting on the arm via a tilting shaft. A first detector is mounted on the frame for detecting a deviation the car-width direction of the jig with respect to the window portion. A pair of second detectors are provided on the frame at positions which are symmetrical with respect to the car width direction center line of the jig for detecting deviations in the plane of the window opening. First, deviation detected by the first detector is corrected by moving the jig in the car width direction. Then, deviation in tilt detected by the second detectors is corrected by tilting the jig. Finally, deviation in height detected jointly by the second detectors is corrected by raising or lowering the jig. Thereafter, the window glass is mounted in the window portion.

摘要翻译： 具有从轿厢主体输送线外侧的位置向车线摆动并且能够沿着车体的长度，宽度和高度方向移动的机器人的机器人设置有承载用于保持窗玻璃的夹具的支撑框架。 框架通过倾斜轴可倾斜地安装在手臂上。 第一检测器安装在框架上，用于检测夹具相对于窗口部分的车宽方向的偏差。 一对第二检测器设置在框架上相对于用于检测窗口开口的平面中的偏差的夹具的车宽方向中心线对称的位置处。 首先，通过在车辆宽度方向上移动夹具来校正由第一检测器检测到的偏差。 然后，通过倾斜夹具来校正由第二检测器检测的倾斜偏差。 最后，通过升高或降低夹具来校正由第二检测器联合检测的高度偏差。 此后，将窗玻璃安装在窗部。