公开(公告)号：US20200091229A1

公开(公告)日：2020-03-19

申请号：US16167485

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

Abstract: A magnetic random access memory (MRAM) includes device strings coupled in parallel, each comprising magnetic tunnel junctions (MTJs) coupled in serial, wherein a quantity of the MTJs of each of the device strings is equal to a quantity of the device strings, and an equivalent resistance (Req) of the MTJs is equal to an average of the sum of a high resistance of one of the MTJs and a low resistance of another MTJ.

公开(公告)号：US20250071983A1

公开(公告)日：2025-02-27

申请号：US18372130

申请日：2023-09-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Yung-Chen Chiu ,  Chih-Kai Kang ,  Wen-Kai Lin

IPC: H10B20/25

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.

公开(公告)号：US20240429228A1

公开(公告)日：2024-12-26

申请号：US18829265

申请日：2024-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A method of manufacturing a resistor-transistor-logic circuit with GaN structures, including steps of forming a GaN layer, an AlGaN barrier layer and a p-type doped GaN capping layer on a substrate, patterning the p-type doped GaN capping layer into multiple p-type doped GaN capping patterns, wherein the GaN layer under parts of the p-type doped GaN capping patterns is converted into gate depletion regions, and the GaN layer not covered by the p-type doped GaN capping patterns in a resistor region functions as 2DEG resistors, forming a passivation layer on the GaN layer and the p-type doped GaN capping patterns, forming multiple sources and drains on the GaN layer, and forming multiple gates on the p-type doped GaN capping patterns, wherein the gates, sources and drains in a high-voltage device region constitute high-voltage HEMTs, and the gates, sources and drains in a low-voltage device region constitute low-voltage logic FETs.

公开(公告)号：US20240387523A1

公开(公告)日：2024-11-21

申请号：US18212188

申请日：2023-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Kun-Szu Tseng ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a substrate. A high voltage transistor is disposed within a high voltage region of the substrate. The high voltage transistor includes a first gate dielectric layer disposed on the substrate. A first gate electrode is disposed on the first gate dielectric layer. A first source/drain doping region and a second source/drain doping region are respectively disposed in the substrate at two sides of the first gate electrode. A first silicide layer covers and contacts the first source/drain doping region and a second silicide layer covers and contacts the second source/drain doping region. A first conductive plate penetrates the first silicide layer and contacts the first source/drain doping region. A second conductive plate penetrates the second silicide layer and contacts the second source/drain doping region.

公开(公告)号：US12133377B2

公开(公告)日：2024-10-29

申请号：US17320234

申请日：2021-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: H10B20/20 ,  G11C17/16

CPC classification number: H10B20/20 ,  G11C17/16

Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

公开(公告)号：US12132043B2

公开(公告)日：2024-10-29

申请号：US18119260

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02

CPC classification number: H01L27/0605 ,  H01L21/30621 ,  H01L21/765 ,  H01L21/8252 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

公开(公告)号：US20240090234A1

公开(公告)日：2024-03-14

申请号：US18512058

申请日：2023-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

IPC: H10B61/00 ,  G11C7/18 ,  H10N50/80

CPC classification number: H10B61/20 ,  G11C7/18 ,  H10N50/80

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

公开(公告)号：US11778814B2

公开(公告)日：2023-10-03

申请号：US17329171

申请日：2021-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

IPC: H10B20/20 ,  H01L29/423 ,  H10B10/00

CPC classification number: H10B20/20 ,  H01L29/42364 ,  H10B10/18

Abstract: A semiconductor device includes a substrate having an input/output (I/O) region, an one time programmable (OTP) capacitor region, and a core region, a first metal gate disposed on the I/O region, a second metal gate disposed on the core region, and a third metal gate disposed on the OTP capacitor region. Preferably, the first metal gate includes a first high-k dielectric layer, the second metal gate includes a second high-k dielectric layer, and the first high-k dielectric layer and the second high-k dielectric layer include an I-shape.

公开(公告)号：US20230247827A1

公开(公告)日：2023-08-03

申请号：US18134041

申请日：2023-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

公开(公告)号：US11705512B2

公开(公告)日：2023-07-18

申请号：US17676799

申请日：2022-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).