公开(公告)号：US5844266A

公开(公告)日：1998-12-01

申请号：US879871

申请日：1997-06-20

Applicant: Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

Inventor： Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract translation: 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散，通过单晶 半导体材料，其通过从沟槽侧壁外延（epi）生长。 该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

公开(公告)号：US5360759A

公开(公告)日：1994-11-01

申请号：US123605

申请日：1993-09-17

Applicant: Reinhard Stengl ,  Wolfgang Hoenlein ,  Volker Lehmann ,  Andreas Spitzer

Inventor： Reinhard Stengl ,  Wolfgang Hoenlein ,  Volker Lehmann ,  Andreas Spitzer

IPC: H01L21/28 ,  H01L21/306 ,  H01L31/11 ,  H01L33/34 ,  H01L21/283 ,  H01L21/265

CPC classification number: H01L33/346 ,  H01L21/306 ,  H01L31/1105 ,  Y10S438/96

Abstract: For manufacturing a component with porous silicon, two highly doped regions with a lightly doped region arranged between them are formed in a silicon wafer. The dopant concentrations are thereby set such that porous silicon arises in the lightly doped region in a subsequent anodic etching. Light-emitting diodes or light-controlled bipolar transistors can be manufactured in this way.

Abstract translation: 为了制造具有多孔硅的部件，在硅晶片中形成具有布置在它们之间的轻掺杂区域的两个高掺杂区域。 因此，掺杂剂浓度被设定为使得随后的阳极蚀刻在轻掺杂区域中产生多孔硅。 可以以这种方式制造发光二极管或光控双极晶体管。

公开(公告)号：US08003475B2

公开(公告)日：2011-08-23

申请号：US12051928

申请日：2008-03-20

Applicant: Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

Inventor： Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

IPC: H01L21/331

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US07968972B2

公开(公告)日：2011-06-28

申请号：US12716692

申请日：2010-03-03

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L29/73

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US20110042046A1

公开(公告)日：2011-02-24

申请号：US12940713

申请日：2010-11-05

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

IPC: F28D15/04 ,  H01L21/306

CPC classification number: H01L23/473 ,  H01L21/30604 ,  H01L21/3063 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract translation: 提供一种集成电路装置及其制造方法。 至少一个集成电子部件布置在基板的主要区域。 该部件布置在基板中，或者通过电绝缘区域与基板隔离。 主通道形成在基板上并且沿着主区域布置。 每个主通道相对于纵向轴线横向地完全被基底包围。 横向通道相对于主通道横向布置。 每个横向通道打开至少一个主通道。 超过十个横向通道进入主通道。

公开(公告)号：US07719088B2

公开(公告)日：2010-05-18

申请号：US11254502

申请日：2005-10-20

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L29/72

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US07285470B2

公开(公告)日：2007-10-23

申请号：US11240297

申请日：2005-09-30

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area (32, 34) of a first conductivity type (p) is provided above a semiconductor substrate (1); a connecting area (40) of the first conductivity type (p ) is provided above the semiconductor area (32, 34); a first insulating area (35″) is provided above the connecting area (40); a window (F) is formed within the first insulating area (35″) and the connecting area (40) so as to at least partly expose the semiconductor area (32, 34); a sidewall spacer (80) is provided in the window (F) in order to insulate the connecting area (40); a second semiconductor area (60) of the second conductivity type (n+) is provided so as to cover the sidewall spacer (80) and a portion of the surrounding first insulating area (35″); the surrounding first insulating area (35″) and the sidewall spacer (80) are removed in order to form a gap (LS) between the connecting area (40) and the second semiconductor area (60); and the gap (LS) is sealed by means of a second insulating area (100) while a gaseous atmosphere or a vacuum atmosphere is provided inside the sealed gap (LS).

Abstract translation: 本发明涉及一种用于制造双极型半导体元件，特别是双极晶体管的方法和相应的双极半导体元件。 本发明的方法包括以下步骤：第一导电类型（p）的第一半导体区域（32,34）设置在半导体衬底（1）的上方; 在半导体区域（32,34）的上方设置第一导电类型（p +）的连接区域（40）。 第一绝缘区域（35“）设置在连接区域40上方; 在第一绝缘区域（35“）和连接区域（40）内形成窗口（F），以便至少部分地暴露半导体区域（32,34）; 在窗口（F）中设置侧壁间隔件（80）以使连接区域（40）绝缘; 提供第二导电类型（n +）的第二半导体区域（60），以覆盖侧壁间隔物（80）和周围的第一绝缘区域（35“）的一部分; 为了在连接区域（40）和第二半导体区域（60）之间形成间隙（LS），除去周围的第一绝缘区域（35“）和侧壁间隔物（80） 并且在所述密封间隙（LS）的内部设置有气氛或真空气氛的同时，所述间隙（LS）借助于第二绝缘区域（100）密封。

公开(公告)号：US20060040453A1

公开(公告)日：2006-02-23

申请号：US11246420

申请日：2005-10-07

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0821 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm−3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region. The carbon-doped semiconductor region prevents an outdiffusion from the zone of the collector region into the remaining region of the collector region.

Abstract translation: 包括第一导电类型的集电极区域和在集电极区域的第一侧的第一导电类型的子集电极区域的双极晶体管。 晶体管还包括设置在集电极区域的第二侧的第二导电类型的基极区域和设置在远离收集区域的一侧的基极区域上方的第一导电类型的发射极区域。 在集电极区域旁边的第一侧设置碳掺杂半导体区域。 双极晶体管的特征在于，碳掺杂半导体区域的碳浓度为10〜20±0.01cm -3，基极 区域具有比集电极区域更小的横截面，并且在与基极区域的重叠区域中具有与剩余区域相比具有增加的掺杂的区域。 碳掺杂半导体区域防止从集电极区域向集电极区域的剩余区域的扩散。

公开(公告)号：US20060038258A1

公开(公告)日：2006-02-23

申请号：US11254502

申请日：2005-10-20

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Hertbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Hertbert Schafer

IPC: H01L27/102

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US06710388B2

公开(公告)日：2004-03-23

申请号：US09801209

申请日：2001-03-07

Applicant: Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

Inventor： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

IPC: H01L27108

CPC classification number: G11C11/22 ,  H01L29/78391

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Abstract translation: 适合作为存储元件的铁电晶体管具有设置在半导体衬底的表面上并设置在源极/漏极区之间的第一栅极中间层和第一栅电极。 第一栅极中间层包含至少一个铁电层。 除了第一栅极中间层之外，在源极/漏极区域之间配置第二栅极中间层和第二栅极电极。 第二栅极中间层包含电介质层。 第一栅电极和第二栅极通过二极管结构彼此连接。