公开(公告)号：US06710388B2

公开(公告)日：2004-03-23

申请号：US09801209

申请日：2001-03-07

申请人： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

发明人： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

IPC分类号： H01L27108

CPC分类号： G11C11/22 ,  H01L29/78391

摘要： A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

摘要翻译： 适合作为存储元件的铁电晶体管具有设置在半导体衬底的表面上并设置在源极/漏极区之间的第一栅极中间层和第一栅电极。 第一栅极中间层包含至少一个铁电层。 除了第一栅极中间层之外，在源极/漏极区域之间配置第二栅极中间层和第二栅极电极。 第二栅极中间层包含电介质层。 第一栅电极和第二栅极通过二极管结构彼此连接。

公开(公告)号：US06469887B2

公开(公告)日：2002-10-22

申请号：US10011133

申请日：2001-11-13

申请人： Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

发明人： Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

IPC分类号： H01G406

CPC分类号： H01L27/1085 ,  H01L21/31604 ,  H01L28/40 ,  H01L28/56

摘要： A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

公开(公告)号：US06548846B2

公开(公告)日：2003-04-15

申请号：US09734466

申请日：2000-12-11

申请人： Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

发明人： Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

IPC分类号： H01L27108

CPC分类号： H01L27/1085 ,  H01L27/10805

摘要： A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

摘要翻译： 用于DRAM的存储电容器具有由氮化硅构成的电介质，并且在电介质上具有彼此相对设置的至少两个电极。 对于电极，使用在材料的费米能级和电介质的导带之间具有高隧道势垒的材料。 用于电极的合适材料是金属如铂，钨和铱或硅化物。

公开(公告)号：US06204119B1

公开(公告)日：2001-03-20

申请号：US09312572

申请日：1999-05-14

申请人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

发明人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  Y10S438/97

摘要： A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

摘要翻译： 集成存储器电路中的电容器的制造方法包括：首先将作为蚀刻停止层的第一导电层和辅助层沉积到载体上。 然后在第一导电层和辅助层的顶部上产生包含第一材料和第二材料的交替层的层序列。 层序列可以具体地具有p + / p-硅层或硅/锗层。 从层序列形成具有要制造的电容器的基极的层结构。 层结构的侧面设置有导电支撑结构。 在层结构内形成一个开口，一直到辅助层，然后除去辅助层和由第二材料制成的层。 由第一材料和支撑结构制成的层的自由表面设置有施加对电极的电容器电介质。

公开(公告)号：US06552385B2

公开(公告)日：2003-04-22

申请号：US09756082

申请日：2001-01-08

申请人： Gerhard Beitel ,  Martin Franosch ,  Thomas Peter Haneder ,  Gerrit Lange ,  Hans Reisinger ,  Herbert Schäfer ,  Stephan Schlamminger ,  Hermann Wendt

发明人： Gerhard Beitel ,  Martin Franosch ,  Thomas Peter Haneder ,  Gerrit Lange ,  Hans Reisinger ,  Herbert Schäfer ,  Stephan Schlamminger ,  Hermann Wendt

IPC分类号： H01L27108

CPC分类号： H01L28/56 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691

摘要： A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

摘要翻译： 描述了包含BaSrTiO 3（BST）电介质的DRAM电容器。 该电介质具有能够形成电子槽的三层结构，其中电子可以永久性地被捕获。

公开(公告)号：US06614066B2

公开(公告)日：2003-09-02

申请号：US10113418

申请日：2002-04-01

申请人： Reinhard Stengl ,  Hans Reisinger ,  Thomas Haneder ,  Harald Bachhofer

发明人： Reinhard Stengl ,  Hans Reisinger ,  Thomas Haneder ,  Harald Bachhofer

IPC分类号： H01L2976

CPC分类号： H01L29/516 ,  H01L29/78391

摘要： A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

公开(公告)号：US6165835A

公开(公告)日：2000-12-26

申请号：US341937

申请日：1999-07-20

申请人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

发明人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L29/66181 ,  Y10S438/96

摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。 出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质 层（4）和导电层（5），而不填充孔结构（2）。 为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面 压缩机械应力。

公开(公告)号：US06215140B1

公开(公告)日：2001-04-10

申请号：US09398691

申请日：1999-09-20

申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC分类号： H01L2972

CPC分类号： H01L21/8229 ,  H01L27/1021

摘要： A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

摘要翻译： 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

公开(公告)号：US6133126A

公开(公告)日：2000-10-17

申请号：US398688

申请日：1999-09-20

申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC分类号： H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

CPC分类号： H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

摘要： A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

摘要翻译： 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

公开(公告)号：US06468348B1

公开(公告)日：2002-10-22

申请号：US09539237

申请日：2000-03-30

申请人： Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

发明人： Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

IPC分类号： C30B2504

CPC分类号： B32B38/10 ,  B82Y20/00 ,  C30B25/00 ,  C30B29/60 ,  G02B6/1225

摘要： An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.

摘要翻译： 在每种情况下制造具有多个二维结构化层的开放形式。 该形式由根据其掺杂可蚀刻的硅制成。 首先制造第一硅层，并且通过掺杂第一层的至少一个区域来标记属于待生产形式的第一层的一部分。 随后，施加至少一个另外的硅层，并且还在其中标记属于该形式的部分。 最后，根据各层的相应掺杂，通过蚀刻去除层的每个未标记部分。 开放形式尤其是光子晶体。