公开(公告)号：US06710388B2

公开(公告)日：2004-03-23

申请号：US09801209

申请日：2001-03-07

申请人： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

发明人： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

IPC分类号： H01L27108

CPC分类号： G11C11/22 ,  H01L29/78391

摘要： A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

摘要翻译： 适合作为存储元件的铁电晶体管具有设置在半导体衬底的表面上并设置在源极/漏极区之间的第一栅极中间层和第一栅电极。 第一栅极中间层包含至少一个铁电层。 除了第一栅极中间层之外，在源极/漏极区域之间配置第二栅极中间层和第二栅极电极。 第二栅极中间层包含电介质层。 第一栅电极和第二栅极通过二极管结构彼此连接。

公开(公告)号：US06469887B2

公开(公告)日：2002-10-22

申请号：US10011133

申请日：2001-11-13

申请人： Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

发明人： Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

IPC分类号： H01G406

CPC分类号： H01L27/1085 ,  H01L21/31604 ,  H01L28/40 ,  H01L28/56

摘要： A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

公开(公告)号：US06204119B1

公开(公告)日：2001-03-20

申请号：US09312572

申请日：1999-05-14

申请人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

发明人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  Y10S438/97

摘要： A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

摘要翻译： 集成存储器电路中的电容器的制造方法包括：首先将作为蚀刻停止层的第一导电层和辅助层沉积到载体上。 然后在第一导电层和辅助层的顶部上产生包含第一材料和第二材料的交替层的层序列。 层序列可以具体地具有p + / p-硅层或硅/锗层。 从层序列形成具有要制造的电容器的基极的层结构。 层结构的侧面设置有导电支撑结构。 在层结构内形成一个开口，一直到辅助层，然后除去辅助层和由第二材料制成的层。 由第一材料和支撑结构制成的层的自由表面设置有施加对电极的电容器电介质。

公开(公告)号：US06894330B2

公开(公告)日：2005-05-17

申请号：US09783187

申请日：2001-02-14

申请人： Harald Bachhofer ,  Georg Braun ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Marc Ullmann

发明人： Harald Bachhofer ,  Georg Braun ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Marc Ullmann

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： G11C11/22

摘要： The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

摘要翻译： 读取或存储存储单元中的铁电晶体管的状态，并且在读取或存储期间在存储矩阵中的另外的存储单元中的另外的铁电晶体管的阈值电压增加或永久地增加。 还提供了包括铁电存储单元的存储器配置。

公开(公告)号：US06798000B2

公开(公告)日：2004-09-28

申请号：US10275337

申请日：2002-12-18

申请人： Richard Johannes Luyken ,  Till Schlösser ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Franz Kreupl

发明人： Richard Johannes Luyken ,  Till Schlösser ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Franz Kreupl

IPC分类号： H01L2976

CPC分类号： H01L51/0595 ,  B82Y10/00 ,  G11C2213/17 ,  H01L51/0048 ,  H01L51/0508 ,  Y10S977/938

摘要： A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.

摘要翻译： 具有纳米线的场效应晶体管，其形成场效应晶体管的源极区，沟道区和漏极区，纳米线是半导体和/或金属导电的纳米线。 场效应晶体管还具有形成场效应晶体管的栅极区域的至少一个纳米管，纳米管是半导体和/或金属导电的纳米管。 纳米线和纳米管彼此间隔一定距离或以这样的方式设置，使得在纳米线和纳米管之间基本上不可能存在隧穿电流，并且纳米线的沟道区的导电性 可以通过施加到纳米管的电压的结果通过场效应来控制。

公开(公告)号：US06441424B1

公开(公告)日：2002-08-27

申请号：US09176558

申请日：1998-10-21

申请人： Helmut Klose ,  Volker Lehmann ,  Hans Reisinger ,  Wolfgang Hönlein

发明人： Helmut Klose ,  Volker Lehmann ,  Hans Reisinger ,  Wolfgang Hönlein

IPC分类号： H01L2994

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L27/10861

摘要： An integrated circuit configuration, in particular is a DRAM cell configuration, includes a capacitor disposed on a first substrate and a portion with a contact disposed on a second substrate. The first substrate is connected to the second substrate, with the contact adjoining the capacitor. The first substrate and the second substrate can be connected essentially in an unadjusted manner, if capacitor elements are distributed over the first substrate and a contact surface of the contact is so large that when the substrates are connected, the contact in each case adjoins at least one of the capacitor elements, which then defines the capacitor. The capacitor may include a plurality of capacitor elements, which makes its capacitance especially high. A method is also provided for producing the integrated circuit configuration.

摘要翻译： 集成电路配置，特别是DRAM单元配置，包括设置在第一基板上的电容器和设置在第二基板上的接触部分。 第一基板连接到第二基板，接触件邻接电容器。 如果电容器元件分布在第一基底上，接触面的接触表面如此大，则当第一基底和第二基底基本上以未调整的方式连接时 电容器元件之一，然后限定电容器。 电容器可以包括多个电容器元件，这使得其电容特别高。 还提供了一种用于产生集成电路配置的方法。

公开(公告)号：US07413971B2

公开(公告)日：2008-08-19

申请号：US10498421

申请日：2002-10-23

申请人： Werner Steinhögl ,  Franz Kreupl ,  Wolfgang Hönlein

发明人： Werner Steinhögl ,  Franz Kreupl ,  Wolfgang Hönlein

IPC分类号： H01L21/44

CPC分类号： H01L21/7682 ,  B82Y10/00 ,  H01L51/0048 ,  H01L2221/1047 ,  Y10S977/742

摘要： An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.

摘要翻译： 公开了一种用于制造电路装置的装置和方法。 该方法包括具有层布置，其中在基板上形成基本上彼此平行延伸的两个导电互连。 至少一个辅助结构形成在基板上并且在两个互连之间并且在第一方向上延伸，该第一方向与互连件的连接轴线成45度到90度之间的角度，相对于两个互连件正交地运行 所述至少一个辅助结构由允许所述至少一个辅助结构从电介质层选择性地去除的材料制成。 介电层形成在两个互连之间，使得至少一个辅助结构至少部分地被电介质层覆盖。

公开(公告)号：US07321097B2

公开(公告)日：2008-01-22

申请号：US10204180

申请日：2001-02-02

申请人： Manfred Engelhardt ,  Wolfgang Hönlein ,  Franz Kreupl

发明人： Manfred Engelhardt ,  Wolfgang Hönlein ,  Franz Kreupl

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H01L21/76843 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H05K3/4076 ,  H01L2924/00

摘要： The invention provides in a preferred embodiment an electronic component comprising a first conductive layer, a non-conductive layer and a second conductive layer. A hole is etched through the non-conductive layer. A nanotube, which is provided in said hole, links the first conductive layer to the second conductive layer in a conductive manner.

摘要翻译： 本发明在优选实施例中提供一种电子部件，其包括第一导电层，非导电层和第二导电层。 通过非导电层蚀刻孔。 设置在所述孔中的纳米管以导电方式将第一导电层与第二导电层连接。

公开(公告)号：US07265376B2

公开(公告)日：2007-09-04

申请号：US10533215

申请日：2003-10-29

申请人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Hönlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Rösner ,  Thomas Schulz ,  Michael Specht

发明人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Hönlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Rösner ,  Thomas Schulz ,  Michael Specht

IPC分类号： H01L35/24 ,  H01L51/00 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7888 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/17 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L27/28 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/057

摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

摘要翻译： 公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。 非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。 电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。 电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入电绝缘层中的电荷载流子的影响。

公开(公告)号：US07709827B2

公开(公告)日：2010-05-04

申请号：US10533550

申请日：2003-10-29

申请人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Hönlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Johannes Richard Luyken ,  Wolfgang Rösner ,  Thomas Schulz ,  Michael Specht

发明人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Hönlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Johannes Richard Luyken ,  Wolfgang Rösner ,  Thomas Schulz ,  Michael Specht

IPC分类号： H01L21/8238

CPC分类号： H01L29/78642 ,  B82Y10/00 ,  H01L27/283 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/775 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

摘要翻译： 本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。 垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。 纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。 中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。