公开(公告)号：US20170271504A1

公开(公告)日：2017-09-21

申请号：US15617099

申请日：2017-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ping Wang ,  Jyh-Shyang Jenq ,  Yu-Hsiang Lin ,  Hsuan-Hsu Chen ,  Chien-Hao Chen ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

公开(公告)号：US09711368B2

公开(公告)日：2017-07-18

申请号：US13862484

申请日：2013-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/308 ,  H01L21/66 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823821 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26 ,  H01L29/66795 ,  H01L29/785

Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.

公开(公告)号：US09312365B2

公开(公告)日：2016-04-12

申请号：US14487103

申请日：2014-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09117909B2

公开(公告)日：2015-08-25

申请号：US14470957

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。

公开(公告)号：US09023708B2

公开(公告)日：2015-05-05

申请号：US13866456

申请日：2013-04-19

Applicant: United Microelectronics Corp.

Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。

公开(公告)号：US20140349476A1

公开(公告)日：2014-11-27

申请号：US13902977

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485

Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

Abstract translation: 本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极， 至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。 用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露金属栅极的部分 并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。

公开(公告)号：US20140308761A1

公开(公告)日：2014-10-16

申请号：US13862484

申请日：2013-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/308 ,  H01L21/66

CPC classification number: H01L21/3086 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823821 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26 ,  H01L29/66795 ,  H01L29/785

Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.

Abstract translation: 提供侧壁图像传送（SIT）处理。 首先，提供基板。 在衬底上形成具有图案的牺牲层。 执行第一测量步骤以测量牺牲层的图案的宽度。 材料层在牺牲层上共形地形成，其中根据第一测量步骤的结果调整材料层的厚度。 然后，各向异性地去除材料层，因此材料层成为牺牲层的侧壁上的间隔物。 最后，去除牺牲层。

公开(公告)号：US20140306272A1

公开(公告)日：2014-10-16

申请号：US13863393

申请日：2013-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/762 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。